IP Library › Granted Patent US 8,829,618
Granted Patent B2
US 8,829,618 · App. 13/288,507 · Granted Sep 9, 2014

ESD protection using diode-isolated gate-grounded NMOS with diode string

Inventors: Ponnarith Pok (Plano, TX); Kyle Schulmeyer (Dallas, TX); Roger A. Cline (Plano, TX); Charvaka Duvvury (Plano, TX)
Assignee: Texas Instruments Incorporated
H01L27/0255H01L29/78H01L27/0274
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Quick Facts
Patent No.
US 8,829,618
App. No.
13/288,507
Granted
Sep 9, 2014
Kind
B2
Abstract

An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Claims (11)

1. An integrated circuit, comprising:

a gate-grounded NMOS ESD device with diode-isolation having an isolation diode in series with a source of a gate-grounded NMOS transistor, where said isolation diode is segmented and placed in close proximity to, and on opposite sides of, a body of said gate-grounded NMOS ESD device; and

a diode string coupled to said gate-grounded NMOS ESD device in a forward biased configuration, where diodes of said diode string are segmented and surround said body of said gate-grounded NMOS ESD device.

2. The integrated circuit of claim 1 where said diode string is composed of between 2 and 4 diodes.

3. The integrated circuit of claim 1 where said diode string is composed of 3 diodes.

4. The integrated circuit of claim 1 where said diode string is electrically coupled in series with said diode-isolation and in parallel with said gate-grounded NMOS ESD device.

5. The integrated circuit of claim 1 where said diode string is electrically coupled in parallel with said gate-grounded NMOS ESD device and in parallel with said diode-isolation.

6. The integrated circuit of claim 1 where a gate of said gate-grounded NMOS ESD device is coupled to ground through a resistor.

7. The integrated circuit of claim 1 where said diode string is composed of a gated diode string.

8. The integrated circuit of claim 1 where a substrate contact diffusion surrounds said diodes and said gate-grounded NMOS ESD device.

9. The integrated circuit of claim 1 where said gate-grounded NMOS ESD device, is a core NMOS transistor, an I/O NMOS transistor, or a drain extended NMOS transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2012
From: POK, PONNARITH; SCHULMEYER, KYLE; CLINE, ROGER A.; DUVVURY, CHARVAKA
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 027731/0419 →
Continuity (2)
Provisional Application 61409598 · Nov 3, 2010
Related Publication 20120112286A1 · May 10, 2012