Semiconductor device and manufacturing method thereof

1. A method of manufacturing a semiconductor device, comprising:

(a) providing a substrate having an active region, an interlayer dielectric layer overlying the substrate and having an opening exposing a portion of the active region, spacers on side surfaces of the opening and a first dielectric layer formed on the exposed active region between the spacers;

(b) forming a self-assembly material layer on surfaces of the spacers and a surface of the first dielectric layer, a portion of the self-assembly material layer on the surface of the first dielectric layer being thinner than portions of the self-assembly material layer on the surfaces of the spacers;

(c) removing the portion of the self-assembly material layer on the surface of the first dielectric layer while maintaining the portions of the self-assembly material layer on the surfaces of the spacers, and removing the first dielectric layer to expose a surface of the active region; and

(d) selectively forming a second dielectric layer on the exposed surface of the active region.

2. The method according to claim 1 , further comprising:

(e) before forming the self-assembly material layer, pre-treating a surface of the interlayer dielectric, the surface of the spacers, and a surface of the first dielectric layer to form dangling bonds on those surfaces.

3. The method according to claim 2 , wherein the pre-treating is conducted using a H 2 SO 4 /H 2 O 2 or SC-2 solution so that the surfaces are formed with —OH termination.

4. The method according to claim 1 , wherein the portion of the self-assembly material layer is a mono-layer of the self-assembly material.

5. The method according to claim 1 , wherein the portion of the self-assembly material and the first dielectric layer are removed using diluted hydrofluoric acid.

6. The method according to claim 1 , wherein the second dielectric layer comprises a high-K dielectric material.

7. The method according to claim 6 , wherein the high-K dielectric material is hafnium oxide.

8. The method according to claim 7 , wherein the hafnium oxide is prepared using HfCl 4 and water vapor as precursors.

9. The method according to claim 7 , wherein the hafnium oxide is prepared using Hf(Obu) 4 and O 2 as precursors.

10. The method according to claim 1 , wherein the self-assembly material is CH 3 (CH 2 ) x CH 2 SiCl 3 , where x is an integer in a range from 6 to 10.

11. The method according to claim 10 , wherein x is 8.

12. The method according to claim 1 , further comprising:

(f) selectively forming a conductive buffer layer on the second dielectric layer using the self-assembly material layer as a mask.

13. The method according to claim 12 , wherein the buffer layer comprises one of titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), alloy of tantalum nitride and aluminum nitride (TaAlN), or alloy of titanium nitride and aluminum nitride (TiAlN).

14. The method according to claim 12 , wherein the conductive buffer layer is formed through Enhanced Atomic Layer Deposition using a titanium-contained precursor and a nitrogen-contained precursor which are plasma-cracked, and during the formation of the buffer layer, the titanium-contained precursor is introduced first.

15. The method according to claim 12 , further comprising:

(g) forming a metal gate on the buffer layer.

16. The method according to claim 14 , wherein the interlayer dielectric layer comprises an upper surface that is substantially flush with an upper surface of the metal gate.

17. The method according to claim 1 , further comprising:

(h) annealing after forming the self-assembly material layer.