IP Library › Granted Patent US 8,836,001
Granted Patent B2
US 8,836,001 · App. 13/494,333 · Granted Sep 16, 2014

Semiconductor device having buried bit line, and method for fabricating the same

Inventors: Eun-Shil Park (Gyeonggi-do, KR); Ju-Hyun Myung (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,836,001
App. No.
13/494,333
Granted
Sep 16, 2014
Kind
B2
Abstract

A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.

Claims (34)

1. A method for fabricating a semiconductor device, comprising:

forming at least one body having two sidewalls by etching a semiconductor substrate;

forming a protective layer having open parts that expose portions of the both sidewalls of the body;

forming a buffer layer that fills the open parts; and

forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer,

wherein the forming of the buried bit line comprises:

forming a conductive layer over an entire surface including the buffer layer; and

performing annealing to silicide the conductive layer, the buffer layer and the body.

2. The method of claim 1 , wherein the forming of the buffer layer includes forming the buffer layer using epitaxial growth.

3. The method of claim 1 , wherein the forming of the buffer layer includes forming a monocrystalline silicon layer through selective epitaxial growth.

4. The method of claim 1 , further comprising

performing a baking process onto surfaces of the exposed portions of the both sidewalls of the body before the forming of the buffer layer.

5. The method of claim 4 , wherein the performing of the baking process is implemented in a hydrogen atmosphere.

6. The method of claim 1 , wherein the forming of the buried bit line comprises:

forming a cobalt layer;

forming a cobalt silicide by performing annealing; and

removing the cobalt layer.

7. The method of claim 1 , wherein the forming of the protective layer comprises:

forming a first protective layer over an entire surface including the body;

forming a second protective layer having a different etching selectivity from the first protective layer on lower portions of the both sidewalls of the body;

forming a third protective layer having a different etching selectivity from the first protective layer on upper portions of the both sidewalls of the body; and

selectively removing the first protective layer exposed between the second and third protective layers.

8. The method of claim 1 , further comprises:

performing plasma doping on the exposed portions of the both sidewalls of the body to form a first source or drain region before the forming of the buffer layer.

9. A method for fabricating a semiconductor device, comprising:

etching a silicon substrate and forming a plurality of silicon bodies that each have a burial region;

forming a protective layer having open parts that expose both sidewalls of the burial regions of the silicon bodies;

forming a silicon-containing buffer layer that fills the open parts;

forming a metal-containing layer over entire surfaces of the silicon bodies including the silicon-containing buffer layer;

forming a metal silicide layer in the burial regions of the silicon bodies by fully siliciding the silicon-containing buffer layer and the burial regions;

removing the metal-containing layer; and

forming a dielectric layer that gap-fills spaces between the plurality of silicon bodies.

10. The method of claim 9 , wherein the forming of the silicon-containing buffer layer includes forming a monocrystalline silicon layer through selective epitaxial growth.

11. The method of claim 9 , wherein the metal silicide layer comprises a cobalt silicide layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2012
From: PARK, EUN-SHIL; MYUNG, JU-HYUN
To: SK HYNIX INC.
Reel/Frame 028359/0674 →
Priority Claims (1)
KR 10-2012-0027834 · Mar 19, 2012 · national
Continuity (1)
Related Publication 20130240965A1 · Sep 19, 2013