Dual EPI CMOS integration for planar substrates
View Patent ↗Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.
1. An integrated circuit structure, comprising:
gate electrodes over both n-type and p-type regions on a substrate; and
silicon germanium carbon (Si(Ge)(C)) regions adjacent the gate electrode over the n-type region in at least defined spaces left by removal of silicon germanium regions.
2. The integrated circuit structure according to claim 1 , wherein the silicon germanium carbon regions abut sidewall spacers on the gate electrode over the n-type region.
3. The integrated circuit structure according to claim 2 , further comprising:
remnants of a patterned hard mask on the sidewall spacers and over the silicon germanium carbon regions.
4. The integrated circuit structure according to claim 3 , wherein the hard mask remnants are formed of silicon nitride.
5. The integrated circuit structure according to claim 4 , wherein the silicon germanium carbon regions are epitaxially grown.
6. An integrated circuit structure, comprising:
gate electrodes over both n-type and p-type regions on a substrate;
silicon germanium (SiGe) regions adjacent the gate electrode over the p-type region;
a patterned hard mask over structures on the p-type region;
remnants of a material for the hard mask on sidewall spacers on the gate electrode over the n-type region; and
regions containing at least silicon and germanium adjacent the gate electrode over the n-type region and under the hard mask remnants.
7. The integrated circuit structure according to claim 6 , wherein the regions containing at least silicon and germanium adjacent the gate electrode over the n-type region and under the hard mask remnants are silicon germanium regions formed concurrently with the silicon germanium regions adjacent the gate electrode over the p-type region.
8. The integrated circuit structure according to claim 6 , wherein the regions containing at least silicon and germanium adjacent the gate electrode over the n-type region and under the hard mask remnants are silicon germanium carbon (Si(Ge)(C)) regions epitaxially grown under the hard mask remnants.
9. The integrated circuit structure according to claim 8 , wherein the hard mask is formed of silicon nitride.
10. The integrated circuit structure according to claim 9 , the regions containing at least silicon and germanium adjacent the gate electrode over the n-type region and under the hard mask remnants fill an area between the sidewall spacers and isolation regions separating the n-type region from adjoining areas.