IP Library › Granted Patent US 8,841,175
Granted Patent B2
US 8,841,175 · App. 13/619,395 · Granted Sep 23, 2014

Vertical trench IGBT and method for manufacturing the same

Inventor: Hidenori Fujii (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,841,175
App. No.
13/619,395
Granted
Sep 23, 2014
Kind
B2
Abstract

A method for manufacturing a vertical trench IGBT includes: forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming a trench passing through the body layer; forming a trench gate in the trench via a gate insulating film; forming a polysilicon film containing an impurity of a first conductivity type on the body layer; diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate.

Claims (25)

1. A method for manufacturing a vertical trench IGBT comprising:

forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type;

forming a trench passing through the body layer;

forming a trench gate in the trench via a gate insulating film;

forming a substantially planar polysilicon film containing an impurity of a first conductivity type on the body layer;

diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and

forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate, wherein

the emitter layer includes a true emitter layer formed in the vicinity of the trench gate, and an exterior emitter layer for extruding the true emitter layer.

2. The method for manufacturing a vertical trench IGBT according to claim 1 , further comprising:

forming a resist film on the polysilicon film in a region whereon the emitter layer is formed;

etching the polysilicon film using the resist film as a mask;

after etching the polysilicon film, injecting an impurity of a second conductivity type into the body layer using the resist film as a mask; and

performing a heat treatment to form a diffusion layer of a second conductivity type on a region of the body layer wherein the impurity of a second conductivity type is implanted.

3. The method for manufacturing a vertical trench IGBT according to claim 1 , wherein a natural oxide film is formed between the body layer and the polysilicon film.

4. The method for manufacturing a vertical trench IGBT according to claim 1 , wherein the polysilicon film is simultaneously formed together with a polysilicon which constitutes the trench gate.

5. The method for manufacturing a vertical trench IGBT according to claim 1 , wherein the polysilicon film is simultaneously formed together with a polysilicon which constitutes an electrode of a capacitor.

6. The method for manufacturing a vertical trench IGBT according to claim 1 , wherein the polysilicon film is simultaneously formed together with a polysilicon resistor.

7. A method for manufacturing a vertical trench IGBT comprising:

forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type;

forming a trench passing through the body layer;

forming a trench gate in the trench via a gate insulating film;

forming a polysilicon film containing an impurity of a first conductivity type on the body layer;

diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and

forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate,

wherein a grain size of the polysilicon film is smaller than a width of the emitter layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT ASSIGNMENT FILED UNDER WRONG APPLICATION NUMBER 13/754,712 PREVIOUSLY RECORDED ON REEL 028963 FRAME 0446. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 14, 2012
From: FUJII, HIDENORI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 029622/0688 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2012
From: FUJII, HIDENORI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 028963/0446 →
Priority Claims (1)
JP 2012-052580 · Mar 9, 2012 · national
Continuity (1)
Related Publication 20130234200A1 · Sep 12, 2013