IP Library › Granted Patent US 8,841,662
Granted Patent B2
US 8,841,662 · App. 12/917,548 · Granted Sep 23, 2014

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Suzunosuke Hiraishi (Kanagawa, JP); Kengo Akimoto (Kanagawa, JP); Junichiro Sakata (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L27/1225
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,841,662
App. No.
12/917,548
Granted
Sep 23, 2014
Kind
B2
Abstract

An object is, in a thin film transistor including an oxide semiconductor layer, to reduce contact resistance between the oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer. The source and drain electrode layers have a stacked-layer structure of two or more layers in which a layer in contact with the oxide semiconductor layer is formed using a metal whose work function is lower than the work function of the oxide semiconductor layer or an alloy containing such a metal. Layers other than the layer in contact with the oxide semiconductor layer of the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

Claims (52)

1. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode layer comprising a first mixed layer, the first mixed layer being in contact with the oxide semiconductor layer; and

a drain electrode layer comprising a second mixed layer, the second mixed layer being in contact with the oxide semiconductor layer,

wherein each of the first mixed layer and the second mixed layer comprises a first metal having a lower work function than the oxide semiconductor layer or an alloy comprising the first metal,

wherein each of the first mixed layer and the second mixed layer comprises a first region and a second region,

wherein the first region is closer to the oxide semiconductor layer than the second region,

wherein each of the first region and the second region comprises the first metal, and

wherein the first region has a larger concentration of the first metal or the alloy than the second region.

2. A semiconductor device according to claim 1 , wherein each of the source electrode layer and the drain electrode layer has a stacked-layer structure.

3. The semiconductor device according to claim 1 , wherein each of the first mixed layer and the second mixed layer is formed by an MOCVD method.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises at least any one of zinc, tin, and gallium.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a depression.

6. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode layer comprising a first mixed layer, the first mixed layer being in contact with the oxide semiconductor layer; and

a drain electrode layer comprising a second mixed layer, the second mixed layer being in contact with the oxide semiconductor layer,

wherein each of the first mixed layer and the second mixed layer comprises a first metal having a lower work function than the oxide semiconductor layer, or an alloy comprising the first metal,

wherein each of the first mixed layer and the second mixed layer comprises a second metal having high heat resistance,

wherein each of the first mixed layer and the second mixed layer comprises a first region and a second region,

wherein the first region is closer to the oxide semiconductor layer than the second region,

wherein each of the first region and the second region comprises the first metal, and

wherein the first region has a larger concentration of the first metal or the alloy than the second region.

7. The semiconductor device according to claim 6 , wherein each of the source electrode layer and the drain electrode layer has a stacked-layer structure.

8. The semiconductor device according to claim 6 , wherein each of the first mixed layer and the second mixed layer is formed by an MOCVD method.

9. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer comprises at least any one of zinc, tin, and gallium.

10. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer comprises a depression.

11. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode layer comprising a first mixed layer, the first mixed layer being in contact with the oxide semiconductor layer; and

a drain electrode layer comprising a second mixed layer, the second mixed layer being in contact with the oxide semiconductor layer,

wherein each of the first mixed layer and the second mixed layer comprises a first metal having a work function lower than an electron affinity of the oxide semiconductor layer, or an alloy comprising the first metal,

wherein each of the first mixed layer and the second mixed layer comprises a first region and a second region,

wherein the first region is closer to the oxide semiconductor layer than the second region,

wherein each of the first region and the second region comprises the first metal, and

wherein the first region has a larger concentration of the first metal or the alloy than the second region.

12. A semiconductor device according to claim 11 , wherein each of the source electrode layer and the drain electrode layer has a stacked-layer structure.

13. The semiconductor device according to claim 11 , wherein each of the first mixed layer and the second mixed layer is formed by an MOCVD method.

14. The semiconductor device according to claim 11 , wherein the oxide semiconductor layer comprises at least any one of zinc, tin, and gallium.

15. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode layer comprising a first mixed layer, the first mixed layer being in contact with the oxide semiconductor layer; and

a drain electrode layer comprising a second mixed layer, the second mixed layer being in contact with the oxide semiconductor layer,

wherein each of the first mixed layer and the second mixed layer comprises a first metal having a work function lower than an electron affinity of the oxide semiconductor layer, or an alloy comprising the first metal,

wherein each of the first mixed layer and the second mixed layer further comprises a second first metal having high heat resistance, and

wherein each of the first mixed layer and the second mixed layer comprises a first region and a second region,

wherein the first region is closer to the oxide semiconductor layer than the second region,

wherein each of the first region and the second region comprises the first metal, and

wherein the first region has a larger concentration of the first metal or the alloy than the second region.

16. The semiconductor device according to claim 15 , wherein each of the source electrode layer and the drain electrode layer has a stacked-layer structure.

17. The semiconductor device according to claim 15 , wherein each of the first mixed layer and the second mixed layer is formed by an MOCVD method.

18. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer comprises at least any one of zinc, tin, and gallium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2010
From: YAMAZAKI, SHUNPEI; HIRAISHI, SUZUNOSUKE; AKIMOTO, KENGO; SAKATA, JUNICHIRO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025457/0349 →
Priority Claims (1)
JP 2009-255272 · Nov 6, 2009 · national
Continuity (1)
Related Publication 20110108833A1 · May 12, 2011