IP Library › Granted Patent US 8,842,465
Granted Patent B2
US 8,842,465 · App. 13/675,328 · Granted Sep 23, 2014

Memory element and memory apparatus

Inventors: Kazutaka Yamane (Kanagawa, JP); Masanori Hosomi (Tokyo, JP); Hiroyuki Ohmori (Kanagawa, JP); Kazuhiro Bessho (Kanagawa, JP); Yutaka Higo (Kanagawa, JP); Tetsuya Asayama (Tokyo, JP); Hiroyuki Uchida (Kanagawa, JP)
Assignee: Sony Corporation
G11C11/161
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Quick Facts
Patent No.
US 8,842,465
App. No.
13/675,328
Granted
Sep 23, 2014
Kind
B2
Abstract

A memory element includes a layered structure. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, and the direction of the magnetization is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer, and includes an anti-ferromagnetic oxide layer formed on any of the at least two ferromagnetic layers. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

Claims (16)

1. A memory element, comprising:

a layered structure including:

a memory layer that has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, the direction of the magnetization being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer,

a magnetization-fixed layer that has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer, and includes an anti-ferromagnetic oxide layer formed on a first ferromagnetic layer of the at least two ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer, and

an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

2. The memory element according to claim 1 , wherein

one of the ferromagnetic layers in the magnetization-fixed layer, which comes into contact with the intermediate layer, includes Co—Fe—B as a magnetic material.

3. The memory element according to claim 1 , wherein

the anti-ferromagnetic oxide layer is a Co—O layer.

4. A memory apparatus, comprising:

a memory element configured to hold information depending on magnetization state of a magnetic material, which includes a layered structure including:

a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on the information, the direction of the magnetization being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer,

a magnetization-fixed layer that has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer, and includes an anti-ferromagnetic oxide layer formed on a first ferromagnetic layer of the at least two ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer, and

an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer,

wherein the layered structure includes an oxide layer, a Co—Fe—B magnetic layer and the non-magnetic layer laminated in the stated order; and

two types of interconnections intersecting each other, sandwiching the memory element, through which the current in the lamination direction flows to the memory element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2013
From: YAMANE, KAZUTAKA; HOSOMI, MASANORI; OHMORI, HIROYUKI; BESSHO, KAZUHIRO; HIGO, YUTAKA; ASAYAMA, TETSUYA; UCHIDA, HIROYUKI
To: SONY CORPORATION
Reel/Frame 029882/0139 →
Priority Claims (1)
JP 2011-263508 · Dec 1, 2011 · national
Continuity (1)
Related Publication 20130163314A1 · Jun 27, 2013