Thin film transistor array panel
A thin film transistor array panel includes: a semiconductor layer disposed on an insulation substrate; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode overlapping the semiconductor layer; a first barrier layer disposed between the source electrode and the semiconductor layer; and a second barrier layer disposed between the drain electrode and the semiconductor layer, wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr).
1. A thin film transistor array panel comprising:
a semiconductor layer disposed on an insulation substrate;
a gate electrode overlapping the semiconductor layer;
a source electrode and a drain electrode overlapping the semiconductor layer;
a first barrier layer disposed between the source electrode and the semiconductor layer;
a second barrier layer disposed between the drain electrode and the semiconductor layer,
a first protection layer disposed on a surface of the source electrode where the first barrier layer is not disposed among surfaces of the source electrode;
a second protection layer disposed on a surface of the drain electrode where the second barrier layer is not disposed among surfaces of the drain electrode, and
wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr) and the first protection layer and the second protection layer include nickel-chromium.
2. The thin film transistor array panel of claim 1 , wherein the semiconductor includes an oxide semiconductor.
3. The thin film transistor array panel of claim 2 , wherein
the source electrode and the drain electrode include at least one of copper, aluminum, and silver.
4. The thin film transistor array panel of claim 3 , wherein
the first barrier layer and the second barrier layer include at least one element selected from vanadium (V), titanium (Ti), zirconium (Zr), aluminum (Al), iron (Fe), indium (In), tantalum (Ta), manganese (Mn), magnesium (Mg), chromium (Cr), molybdenum (Mo), cobalt (Co), nickel (Ni), tin (Sn), tungsten (W), niobium (Nb), and neodymium (Nd).
5. The thin film transistor array panel of claim 4 further comprising,
a third barrier layer disposed under the gate electrode,
wherein the gate electrode includes at least one of copper, aluminum, and silver, and wherein the third barrier layer includes nickel-chromium.
6. The thin film transistor array panel of claim 5 , further comprising
a third passivation layer disposed on the gate electrode, and
wherein the third passivation layer includes nickel-chromium.
7. The thin film transistor array panel of claim 1 , wherein
the source electrode and the drain electrode include at least one of copper, aluminum, and silver.
8. The thin film transistor array panel of claim 7 , wherein
the first barrier layer and the second barrier layer include at least one element selected from vanadium (V), titanium (Ti), zirconium (Zr), aluminum (Al), iron (Fe), indium (In), tantalum (Ta), manganese (Mn), magnesium (Mg), chromium (Cr), molybdenum (Mo), cobalt (Co), nickel (Ni), tin (Sn), tungsten (W), niobium (Nb), and neodymium (Nd).
9. The thin film transistor array panel of claim 8 further comprising,
a third barrier layer disposed under the gate electrode,
wherein the gate electrode includes at least one of copper, aluminum, and silver, and wherein the third barrier layer includes nickel-chromium.
10. The thin film transistor array panel of claim 9 , further comprising
a third passivation layer disposed on the gate electrode, and
the third passivation layer includes nickel-chromium.
11. The thin film transistor array panel of claim 1 , wherein
the first barrier layer and the second barrier layer include at least one element selected from vanadium (V), titanium (Ti), zirconium (Zr), aluminum (Al), iron (Fe), indium (In), tantalum (Ta), manganese (Mn), magnesium (Mg), chromium (Cr), molybdenum (Mo), cobalt (Co), nickel (Ni), tin (Sn), tungsten (W), niobium (Nb), and neodymium (Nd).
12. The thin film transistor array panel of claim 11 further comprising,
a third barrier layer disposed under the gate electrode,
wherein the gate electrode includes at least one of copper, aluminum, and silver, and wherein the third barrier layer includes nickel-chromium.
13. The thin film transistor array panel of claim 12 , further comprising
a third passivation layer disposed on the gate electrode, and
the third passivation layer includes nickel-chromium.
14. The thin film transistor array panel of claim 1 further comprising,
a third barrier layer disposed under the gate electrode,
wherein the gate electrode includes at least one of copper, aluminum, and silver, and wherein the third barrier layer includes nickel-chromium.
15. The thin film transistor array panel of claim 14 further comprising
a third passivation layer disposed on the gate electrode, and
the third passivation layer includes nickel-chromium.