IP Library Granted Patent US 8,853,713
Granted Patent B2
US 8,853,713 · App. 13/465,166 · Granted Oct 7, 2014

Resistive memory having confined filament formation

Inventors: Eugene P. Marsh (Boise, ID); Jun Liu (Boise, ID)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,853,713
App. No.
13/465,166
Granted
Oct 7, 2014
Kind
B2
Abstract

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

Claims (34)

1. A method of processing a resistive memory cell, comprising:

forming an opening in a stack having a resistive memory material, a silicon material on the resistive memory material, and a first oxide material on the silicon material; and

forming a second oxide material in the opening adjacent the silicon material by:

selectively forming a metal material in the opening adjacent the silicon material and in contact with the resistive memory material and adjacent a lower portion of the opening; and

oxidizing all of the metal material;

wherein the second oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the second oxide material formed in the opening.

2. The method of claim 1 , wherein the method includes forming an ion source material in the opening adjacent the oxidized metal material and the first oxide material.

3. A method of processing a resistive memory cell, comprising:

forming an opening in a stack having a silicon material and a first oxide material on the silicon material;

forming a second oxide material in the opening adjacent the silicon material by oxidizing the silicon material adjacent the opening such that a portion of the silicon material is consumed, wherein the second oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the second oxide material formed in the opening; and

forming an ion source material in the opening adjacent the first oxide material and the second oxide material, wherein the ion source material is copper telluride or silver sulfide.

4. The method of claim 1 , wherein:

the silicon material is silicon nitride; and

the second oxide material adjacent the silicon material is copper oxide.

5. The method of claim 3 , wherein:

the silicon material is silicon; and

the second oxide material adjacent the silicon material is silicon dioxide.

6. The method of claim 3 , wherein the second oxide material adjacent the silicon material is an annular shaped oxide material.

7. A method of processing a resistive memory cell, comprising:

forming an opening in a vertical stack having a resistive memory material, a silicon material on the resistive memory material, and an oxide material on the silicon material;

selectively forming a metal material in the opening adjacent the silicon material and in contact with the resistive memory material and adjacent a lower portion of the opening;

oxidizing all of the metal material, wherein oxidizing the metal material forms a metal oxide material in the opening adjacent the silicon material and on the resistive memory material that confines filament formation in the resistive memory cell to an area enclosed by the metal oxide material; and

forming an ion source material in the opening on the resistive memory material and adjacent the metal oxide material and the oxide material.

8. The method of claim 7 , wherein the method includes selectively forming the metal material in the opening using a selective atomic layer deposition process.

9. The method of claim 7 , wherein selectively forming the metal material in the opening includes forming the metal material in the opening such that metal material is formed exclusively adjacent the silicon material in contact with the resistive memory material and adjacent the lower portion of the opening.

10. The method of claim 7 , wherein the resistive memory material is zirconium dioxide.

11. A method of processing a resistive memory cell, comprising:

forming an opening in a vertical stack having an electrode, a silicon material on the electrode, and an oxide material on the silicon material;

oxidizing the silicon material adjacent the opening such that a portion of the silicon material is consumed, wherein oxidizing the silicon material adjacent the opening forms a silicon dioxide material in the opening adjacent the silicon material and on the electrode that confines filament formation in the resistive memory cell to an area enclosed by the silicon dioxide material;

forming a resistive memory material in the opening on the electrode and adjacent the silicon dioxide material and the oxide material; and

forming an ion source material in the opening adjacent the resistive memory material and in the area enclosed by the silicon dioxide material, wherein the ion source material is copper telluride or silver sulfide.

12. The method of claim 11 , wherein the oxide material is silicon dioxide.

13. The method of claim 11 , wherein the oxide material is zirconium dioxide.

14. The method of claim 11 , wherein the opening has a width equal to one feature width; wherein one feature width is equal to a total width of the ion source material and the resistive memory material in the opening.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2012
From: MARSH, EUGENE P.; LIU, JUN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028164/0053 →
Continuity (1)
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