Scan compression architecture with bypassable scan chains for low test mode power

1. An integrated circuit comprising:

at least one integrated circuit input terminal;

at least one integrated circuit output terminal;

a plurality of scan chain circuits, each scan chain circuit including

an input multiplexer having a first input receiving a constant digital signal, a second input connected to said at least one integrated circuit input terminal, an output and a control input receiving a corresponding control signal, said input multiplexer connecting said first input or said second input to said output dependent upon said control signal received at said control input;

a serial scan chain of a plurality of bits having an input connected to said output of said input multiplexer and an output, each serial scan chain operable in a test mode to serially connect corresponding bits of an operational circuit of said integrated circuit;

a bypass flip-flop of one bit having an input connected to said at least one integrated circuit input terminal and an output;

an output multiplexer having a first input connected to said output of said bypass flip-flop, a second input connected to said output of said serial scan chain, an output connected to said at least one integrated circuit output terminal and a control input receiving said corresponding control signal, said output multiplexer connecting said first input or said second input to said output dependent upon said control signal received at said control input.

2. The integrated circuit of claim 1 , further comprising:

a decompressor having at least one input connected to said at least one integrated circuit input terminal and a plurality of outputs, each output connected to said second input of said input multiplexer of a corresponding one of said scan chain circuits, wherein said plurality of scan chain circuits are greater in number than said at least one integrated circuit input terminal and said decompressor decompresses data received from said at least one integrated circuit input terminal into signals supplied to said greater number of said scan chain circuits; and

a compactor having a plurality of inputs, each input connected to said output of a corresponding one of said plurality of scan chain circuits and at least one output connected to said at least one integrated circuit output terminal, wherein said at least one integrated circuit output terminal are fewer in number than said plurality of scan chain circuits and said compactor compacts data received from said plurality of scan chain circuits into signals supplied to said fewer number of said at least one integrated circuit input terminal.

3. The integrated circuit of claim 1 , wherein:

said plurality of scan chain circuits are divided into at least two groups; and

a corresponding control signal is separately supplied to said control inputs of said input multiplexer and said output multiplexer of each of said at least two groups of scan chain circuits.

4. A method of testing an integrated circuit comprising the steps of:

supplying each of a first plurality of data streams to a corresponding plurality of scan chain circuits;

for each scan chain circuit selectively scanning in the corresponding data stream to a single bit flip-flop or to a plural bit serial scan chain serially connecting corresponding bits of an operational circuit of said integrated circuit in a test mode, choosing a number of plural bit serial scan chains for selectively scanning in the corresponding data stream to meet a power consumption goal;

operating the operational circuit for at least one clock cycle;

for each scan chain circuit selectively scanning out data stored in the corresponding serial scan chain in the test mode;

comparing the scanned out data with expected data.

5. The method of testing the integrated circuit of claim 4 , further comprising the steps of:

supplying a test pattern to the integrated circuit via a second plurality of integrated circuit input pins;

decompressing the test pattern into said first plurality of data streams, said first plurality being greater than said second plurality;

compacting scanned out data from said first plurality of scan chain circuits into a third plurality of output data streams output via the third plurality of integrated circuit output pins.

6. The method of testing the integrated circuit of claim 5 , further comprising the step of:

automatically generating the test pattern.

7. The method of testing the integrated circuit of claim 4 , wherein:

said step of selectively scanning in the corresponding data stream to the single bit flip-flop or to the plural bit serial scan chain sequentially selects less than all the plural bit serial scan chains in each of a plurality of tests, the subsets selected whereby a finite sequence selects all serial scan chains.