Sub-numa clustering
Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
1. A method comprising:
grouping a plurality of cores of a processor and a plurality of cache slices co-located with the plurality of cores into a first cluster among a plurality of clusters;
partitioning a memory space into a plurality of address regions;
associating each of the plurality of the clusters with a corresponding address region of the plurality of address regions, wherein each memory address of each address region is mapped to at least one of the plurality of cache slices grouped into each of the plurality of the clusters; and
biasing a cache access from one or more of the plurality of cores grouped into the plurality of the clusters based on the address regions corresponding to the clusters, such that the cache access is performed on a selected one of the address regions selected based on which cluster the cache access came from.
2. The method of claim 1 , further comprising: storing data required by a core grouped into the first cluster in the address region associated with the first cluster.
3. The method of claim 1 , further comprising: storing data required by a core grouped into the first cluster in an address region associated with a second cluster, wherein the second cluster is a cluster physically closest to the first cluster.
4. The method of claim 1 , wherein the address region associated with the first cluster includes a contiguous block of memory space.
5. The method of claim 1 , wherein the each memory address of the address region associated with the first cluster is evenly hashed across the plurality of cache slices grouped into the first cluster.
6. The method of claim 1 , wherein the first cluster is visible to an operating system as a NUMA node.
7. The method of claim 1 , further comprising: assigning at least one memory controller to the address region associated with the first cluster, wherein the at least one memory controller assigned to the address region associated with the first cluster manages data flow to and from the address region associated with the first cluster.
8. The method of claim 7 , wherein the at least one memory controller includes a memory controller physically closest to the address region associated with the first cluster.
9. An apparatus comprising:
a processor to execute computer instructions, wherein a plurality of cores of the processor and a plurality of cache slices co-located with the plurality of cores are grouped into a first cluster among a plurality of clusters, and the processor is configured to:
partition a memory space into a plurality of address regions,
associate each of the plurality of the clusters with a corresponding address region of the plurality of address regions, wherein each memory address of each address region is mapped to at least one of the plurality of cache slices grouped into each of the plurality of the clusters, and
bias a cache access from one or more of the plurality of cores grouped into the plurality of the clusters based on the address regions corresponding to the clusters, such that the cache access is performed on a selected one of the address regions selected based on which cluster the cache access came from.
10. The apparatus of claim 9 , wherein the processor is further configured to store data required by a core grouped into the first cluster in the address region associated with the first cluster.
11. The apparatus of claim 9 , wherein the processor is further configured to store data required by a core grouped into the first cluster in an address region associated with a second cluster, wherein the second cluster is a cluster physically closest to the first cluster.
12. The apparatus of claim 9 , wherein the address region associated with the first cluster includes a contiguous block of memory space.
13. The apparatus of claim 9 , wherein the each memory address of the address region associated with the first cluster is evenly hashed across the plurality of cache slices grouped into the first cluster.
14. The apparatus of claim 9 , wherein the first cluster is visible to an operating system as a NUMA node.
15. The apparatus of claim 9 , wherein the processor is further configured to assign at least one memory controller to the address region associated with the first cluster, wherein the at least one memory controller assigned to the address region associated with the first cluster manages data flow to and from the address region associated with the first cluster.
16. The apparatus of claim 15 , wherein the at least one memory controller includes a memory controller physically closest to the address region associated with the first cluster.
17. An apparatus comprising:
a processor to execute computer instructions, wherein a plurality of cores of the processor and a plurality of cache slices co-located with the plurality of cores are grouped into a first cluster among a plurality of clusters; and
a memory,
wherein the memory is partitioned into a plurality of address regions,
each of the plurality of the clusters is associated with a corresponding address region of the plurality of address regions, each memory address of each address region is mapped to at least one of the plurality of cache slices grouped into each of the plurality of the clusters, and
a cache access from one or more of the plurality of cores grouped into the plurality of the clusters is biased based on the address regions corresponding to the clusters, such that the cache access is performed on a selected one of the address regions selected based on which cluster the cache access came from.
18. The apparatus of claim 17 , wherein data required by a core grouped into the first cluster is stored in the address region associated with the first cluster.
19. The apparatus of claim 17 , wherein data required by a core grouped into the first cluster is stored in an address region associated with a second cluster, wherein the second cluster is a cluster physically closest to the first cluster.
20. The apparatus of claim 17 , wherein the address region associated with the first cluster includes a contiguous block of memory space.
21. The apparatus of claim 17 , wherein the each memory address of the address region associated with the first cluster is evenly hashed across the plurality of cache slices grouped into the first cluster.
22. The apparatus of claim 17 , wherein the first cluster is visible to an operating system as a NUMA node.
23. The apparatus of claim 17 , further comprising: at least one memory controller assigned to the address region associated with the first cluster, wherein the at least one memory controller manages data flow to and from the address region associated with the first cluster.
24. The apparatus of claim 23 , wherein the at least one memory controller includes a memory controller physically closest to the address region associated with the first cluster.
25. A non-transitory machine-readable medium having stored thereon an instruction, which if performed by a machine causes the machine to perform a method comprising:
grouping a plurality of cores of a processor and a plurality of cache slices co-located with the plurality of cores into a first cluster among a plurality of clusters;
partitioning a memory space into a plurality of address regions;
associating each of the plurality of the clusters with a corresponding address region of the plurality of address regions, wherein each memory address of each address region is mapped to at least one of the plurality of cache slices grouped into each of the plurality of the clusters; and
biasing a cache access from one or more of the plurality of cores grouped into the plurality of the clusters based on the address regions corresponding to the clusters, such that the cache access is performed on a selected one of the address regions selected based on which cluster the cache access came from.
26. The machine-readable medium of claim 25 , the method further comprising: storing data required by a core grouped into the first cluster in the address region associated with the first cluster.
27. The machine-readable medium of claim 25 , the method further comprising: storing data required by a core grouped into the first cluster in an address region associated with a second cluster, wherein the second cluster is a cluster physically closest to the first cluster.
28. The machine-readable medium of claim 25 , wherein the address region associated with the first cluster includes a contiguous block of memory space.
29. The machine-readable medium of claim 25 , wherein the each memory address of the address region associated with the first cluster is evenly hashed across the plurality of cache slices grouped into the first cluster.
30. The machine-readable medium of claim 25 , wherein the first cluster is visible to an operating system as a NUMA node.
31. The machine-readable medium of claim 25 , the method further comprising: assigning at least one memory controller to the address region associated with the first cluster, wherein the at least one memory controller assigned to the address region associated with the first cluster manages data flow to and from the address region associated with the first cluster.
32. The machine-readable medium of claim 31 , wherein the at least one memory controller includes a memory controller physically closest to the address region associated with the first cluster.