IP Library Granted Patent US 8,872,609
Granted Patent B2
US 8,872,609 · App. 13/203,403 · Granted Oct 28, 2014

Inductor element and integrated circuit device

Inventor: Tadahiro Kuroda (Kanagawa, JP)
Assignee: Keio University
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Quick Facts
Patent No.
US 8,872,609
App. No.
13/203,403
Granted
Oct 28, 2014
Kind
B2
Abstract

The invention relates to an inductor element and an integrated circuit device where the efficiency of use of wire materials is high and noise interference through capacitive/inductive coupling from peripheral wires is low. Coil elements 1, 2 are provided in at least two adjacent layer levels having main wires which run in different directions so that each coil element 1 ( 2 ) is connected to a coil element 2 ( 1 ) in a different layer level so as to form one coil, and shield wires 3, 4 are connected to a power 5 either above or below or to the left or right of said coil elements 1, 2.

Claims (36)

1. An integrated circuit device, comprising:

a coil comprising

a plurality of first metal coil elements running in a first direction on a first layer level;

a plurality of second metal coil elements running, in a second direction different from the first direction, on the second layer level adjacent to the first layer level,

wherein the first metal coil elements and the second metal coil elements are connected to form the coil;

shield wires connected to a power either above or below or to the left or right of the first metal coil elements and the second metal coil elements, and

a wiring, running on the first layer level between the first metal coil elements, or running on the second layer level between the second metal coil elements.

2. The integrated circuit device according to claim 1 , wherein said shield wires do not form a closed loop.

3. An integrated circuit device, comprising:

a coil comprising

a plurality of first metal coil elements running in a first direction on a first layer level;

a plurality of second metal coil elements running, in a second direction different from the first direction, on the second layer level adjacent to the first layer level,

wherein the first metal coil elements and the second metal coil elements are connected to form the coil; and

a wiring, running on the first layer level between the first metal coil elements, or running on the second layer level between the second metal coil elements,

wherein either a region where a wire is prohibited from being layered on the coil elements adjacent to as well as above or below said coil elements or a region where wiring is prohibited in the same plane with said coil elements so that the region can be provided with one to three peripheral wires to the right or left of said coil wires.

4. An integrated circuit device, comprising:

a coil comprising

a plurality of first metal coil elements running in a first direction on a first layer level;

a plurality of second metal coil elements running, in a second direction different from the first direction, on the second layer level adjacent to the first layer level,

wherein the first metal coil elements and the second metal coil elements are connected to form the coil; and

a wiring, running on the first layer level between the first metal coil elements, or running on the second layer level between the second metal coil elements,

wherein extended coil elements which extend from two terminals of said coil.

5. An integrated circuit device, comprising:

a coil comprising

a plurality of first metal coil elements running in a first direction on a first layer level;

a plurality of second metal coil elements running, in a second direction different from the first direction, on the second layer level adjacent to the first layer level,

wherein the first metal coil elements and the second metal coil elements are connected to form the coil; and

a wiring, running on the first layer level between the first metal coil elements, or running on the second layer level between the second metal coil elements,

wherein the potential at the center of said coil is fixed.

6. An integrated circuit device, comprising:

a plurality of coils comprising

a plurality of first metal coil elements running in a first direction on a first layer level;

a plurality of second metal coil elements running, in a second direction different from the first direction, on the second layer level adjacent to the first layer level,

wherein the first metal coil elements and the second metal coil elements are connected to form the coil; and

a wiring, running on the first layer level between the first metal coil elements, or running on the second layer level between the second metal coil elements,

wherein the coils have similarity shapes having a point of symmetry and are placed around the point of symmetry, and at the same time the coils are arranged in such a manner that each coil in the next layer is rotated in a direction around the point of symmetry and connected in series.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2016
From: KEIO UNIVERSITY
To: THRUCHIP JAPAN, INC.
Reel/Frame 039549/0288 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: KURODA, TADAHIRO
To: KEIO UNIVERSITY
Reel/Frame 026837/0089 →
Priority Claims (1)
JP 2009-042134 · Feb 25, 2009 · national
Continuity (1)
Related Publication 20110309907A1 · Dec 22, 2011