IP Library › Granted Patent US 8,872,751

Granted Patent B2

US 8,872,751 · App. 12/730,952 · Granted Oct 28, 2014

Liquid crystal display device having interconnected transistors and electronic device including the same

Inventors: Hajime Kimura (Kanagawa, JP); Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G09G3/3688 G09G3/20 G09G2310/0286 G09G2300/0842 G09G2310/0267 G09G2310/0275 G09G2310/0291 G09G2300/0426

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Quick Facts

Patent No.: US 8,872,751
App. No.: 12/730,952
Granted: Oct 28, 2014
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A driver circuit includes a circuit 200 , a transistor 101 — 1, and a transistor 101 — 2 . A signal is selectively input from the circuit 200 to a gate of the transistor 101 — 1 and the transistor 101 — 2, so that the transistor 101 — 1 and the transistor 101 — 2 are controlled to be on or off. The transistor 101 — 1 and the transistor 101 — 2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

Claims (126)

1. A liquid crystal display device comprising:

a driver circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; and

a pixel comprising a liquid crystal element,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,

wherein a gate of the second transistor is electrically connected to the gate of the first transistor,

wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to a first line,

wherein a gate of the sixth transistor is electrically connected to a second line,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor, and

wherein on and off of both the first transistor and the second transistor are configured to be controlled by a first input signal input to both the gate of the first transistor and the gate of the second transistor.

2. The liquid crystal display device according to claim 1 , wherein a channel width of the third transistor is equal to a channel width of the fourth transistor.

3. The liquid crystal display device according to claim 1 ,

wherein a channel width of the first transistor is smaller than a channel width of the third transistor, and

wherein a channel width of the second transistor is smaller than a channel width of the fourth transistor.

4. An electronic device comprising at least the liquid crystal display device according to claim 1 and an operation switch for controlling operation of the liquid crystal display device.

5. The liquid crystal display device according to claim 1 ,

wherein a second input signal is input to the gate of the fifth transistor,

wherein a third input signal is input to the gate of the sixth transistor,

wherein a fourth input signal is input to the one of the source and the drain of the third transistor,

wherein the fourth input signal is input to the one of the source and the drain of the fourth transistor,

wherein an output signal is output from the other of the source and the drain of the third transistor, and

wherein the output signal is output from the other of the source and the drain of the fourth transistor.

6. The liquid crystal display device according to claim 1 ,

wherein the gate of the first transistor is electrically connected to a third line,

wherein the gate of the second transistor is electrically connected to the third line,

wherein the one of the source and the drain of the third transistor is electrically connected to a fourth line,

wherein the one of the source and the drain of the fourth transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth line, and

wherein the one of the source and the drain of the fourth transistor is electrically connected to the fifth line.

7. The liquid crystal display device according to claim 1 ,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth line, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to the sixth line.

8. The liquid crystal display device according to claim 1 ,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth line, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to a seventh line.

9. The liquid crystal display device according to claim 1 ,

wherein a clock signal is input to the one of the source and the drain of the third transistor,

wherein the clock signal is input to the one of the source and the drain of the fourth transistor,

wherein an output signal is output from the other of the source and the drain of the third transistor, and

wherein the output signal is output from the other of the source and the drain of the fourth transistor.

10. A liquid crystal display device comprising:

a driver circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; and

a pixel comprising a liquid crystal element,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,

wherein a gate of the second transistor is electrically connected to the gate of the first transistor,

wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to the gate of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the fourth transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the third transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a first line,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a second line, and

11. The liquid crystal display device according to claim 10 , wherein a channel width of the third transistor is equal to a channel width of the fourth transistor.

12. The liquid crystal display device according to claim 10 ,

wherein a channel width of the first transistor is smaller than a channel width of the third transistor, and

wherein a channel width of the second transistor is smaller than a channel width of the fourth transistor.

13. An electronic device comprising at least the liquid crystal display device according to claim 10 and an operation switch for controlling operation of the liquid crystal display device.

14. The liquid crystal display device according to claim 10 ,

wherein a second input signal is input to the other of the source and the drain of the fifth transistor,

wherein a third input signal is input to the other of the source and the drain of the sixth transistor,

wherein a fourth input signal is input to the one of the source and the drain of the third transistor,

wherein the fourth input signal is input to the one of the source and the drain of the fourth transistor,

wherein an output signal is output from the other of the source and the drain of the third transistor, and

wherein the output signal is output from the other of the source and the drain of the fourth transistor.

15. The liquid crystal display device according to claim 10 ,

wherein the gate of the first transistor is electrically connected to a third line,

wherein the gate of the second transistor is electrically connected to the third line,

wherein the one of the source and the drain of the third transistor is electrically connected to a fourth line,

wherein the one of the source and the drain of the fourth transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth line, and

wherein the one of the source and the drain of the fourth transistor is electrically connected to the fifth line.

16. The liquid crystal display device according to claim 10 ,

wherein a clock signal is input to the one of the source and the drain of the third transistor,

wherein the clock signal is input to the one of the source and the drain of the fourth transistor,

wherein an output signal is output from the other of the source and the drain of the third transistor, and

wherein the output signal is output from the other of the source and the drain of the fourth transistor.

17. A liquid crystal display device comprising: