Non-volatile memory device with single-polysilicon-layer memory cells
An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.
1. A non-volatile memory cell, comprising:
a first well region;
first and second source-drain regions disposed in the well region;
a first body region disposed in the well region between the first and second source-drain regions;
first and second program-erase regions; and
a floating gate disposed over the body region and the first and second program-erase regions, the floating gate configured to acquire a program charge in response to a first voltage on the first well region and the first program-erase region and a second voltage on the second program-erase region, and to acquire an erase charge in response to a third voltage on the first well region and the second program-erase regions and a fourth voltage on the first program-erase region.
2. The non-volatile memory cell of claim 1 , further comprising an insulator disposed between the floating gate and the first and second drain regions, the body region, and the first and second program-erase regions.
3. The non-volatile memory cell of claim 1 wherein:
the first well region has a first type of conductivity;
the first and second source-drain regions have a second type of conductivity;
the first program-erase region has the first type of conductivity; and
the second program-erase region has the second type of conductivity.
4. The non-volatile memory cell of claim 1 wherein:
the first well region has a P-type conductivity;
the first and second source-drain regions have an N-type conductivity;
the body region has a P-type conductivity;
the first program-erase region has a P-type conductivity; and
the second program-erase region has an N-type conductivity.
5. The non-volatile memory cell of claim 1 wherein:
the third voltage equals the second voltage; and
the fourth voltage equals the first voltage.
6. The non-volatile memory cell of claim 1 , further comprising:
a second well region of a first type of conductivity;
the first well region and a third well region disposed in the second well region and of a second type of conductivity;
wherein the first program-erase region is disposed in the second well region and is of the second type of conductivity; and
wherein the second program-erase region is disposed in the third well region and is of the first type of conductivity.
7. The non-volatile memory cell of claim 1 , further comprising:
a second well region of a first type of conductivity;
the first well region and a third well region disposed in the second well region and of a second type of conductivity;
wherein the first program-erase region is disposed in the second well region and is of the second type of conductivity;
wherein the second program-erase region is disposed in the third well region and is of the first type of conductivity; and
wherein the floating gate includes a first portion disposed a first distance over the body region, a second portion disposed a second distance over the second well region, a third portion disposed approximately the first distance over the first program-erase region, a fourth portion disposed approximately the second distance over the third well region, and a fifth portion disposed approximately the first distance over the second program-erase region.
8. The non-volatile memory cell of claim 1 , further comprising:
a third source-drain region;
a second body region disposed in the first well region between the second and third source-drain regions; and
an access gate disposed over the second body region.
9. An integrated circuit, comprising:
an array of non-volatile memory cells, at least one of non-volatile memory cell including
a well region;
first and second source-drain regions disposed in the well region;
a body region disposed in the well region between the first and second source-drain regions;
first and second program-erase regions; and
a floating gate disposed over the body region and the first and second program-erase regions, the floating gate configured to acquire a program charge in response to a first voltage on the well region and the first program-erase region and a second voltage on the second program-erase region, and to acquire an erase charge in response to a third voltage on the well region and the second program-erase region and a fourth voltage on the first program-erase region.
10. The integrated circuit of claim 9 , further comprising:
a row decoder coupled to the array;
a column decoder coupled to the array;
a read-write unit coupled to the array; and
a program-erase circuit coupled to the array.
11. A system, comprising:
a first integrated circuit, including
an array of non-volatile memory cells, at least one of non-volatile memory cell including
a well region;
first and second source-drain regions disposed in the well region,
a body region disposed in the well region between the first and second source-drain regions;
first and second program-erase regions, and
a floating gate disposed over the body region and the first and second program-erase regions, the floating gate configured to acquire a program charge in response to a first voltage on the well region and the first program-erase region and a second voltage on the second program-erase region, and to acquire an erase charge in response to a third voltage on the well region and second program-erase region and a fourth voltage on the first program-erase region; and
a second integrated circuit coupled to the first integrated circuit.
12. The system of claim 11 wherein at least one of the first and second integrated circuits includes a computing circuit.
13. The system of claim 11 wherein the first and second integrated circuits are disposed on a same die.
14. The system of claim 11 wherein the first and second integrated circuits are disposed on respective dies.
15. A method, comprising:
coupling a first voltage to respective first nodes of first and second capacitors that include a floating gate of a non-volatile memory cell as a common second node;
coupling a second voltage to a respective first node of a third capacitor that includes the floating gate as a second node; and
changing a threshold voltage of the non-volatile memory cell in response to the first and second voltages.
16. The method of claim 15 wherein changing the threshold voltage includes programming the non-volatile memory cell.
17. The method of claim 15 wherein changing the threshold voltage includes erasing the non-volatile memory cell.
18. The method of claim 15 wherein:
the first voltage is higher than the second voltage; and
changing the threshold voltage includes programming the non-volatile memory cell.
19. The method of claim 15 wherein:
the first voltage is lower than the second voltage; and
changing the threshold voltage includes erasing the non-volatile memory cell.
20. The method of claim 15 wherein changing the threshold voltage includes changing an amount of charge on the floating gate.
21. A non-volatile memory cell, comprising:
a first well region;
a second well region spaced apart from the first well region;
first and second source-drain regions disposed in the first well region;
a body region disposed in the first well region between the first and second source-drain regions;
a first program-erase region disposed in the second well region; and
a floating gate having a first portion disposed a first distance over the body region, a second portion disposed a second distance over the second well region, and a third portion disposed approximately the first distance over the first program-erase region, the second distance greater than the first distance.
22. The non-volatile memory cell of claim 21 , further comprising an insulator disposed between the floating gate and the first and second well regions.
23. The non-volatile memory cell of claim 21 , further comprising:
a third well region;
wherein the first and second well regions are disposed in the third well region;
a second program-erase region disposed in the third well region between the first and second well regions; and
wherein the floating gate has a fourth portion disposed approximately the second distance over the third well region between the first and second well regions and having a fifth portion disposed approximately the first distance over the second program-erase region.