Thin film transistors and methods for manufacturing the same
Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.
1. A thin film transistor, comprising:
a gate electrode on a substrate;
a gate dielectric layer on the gate electrode and the substrate;
a source/drain electrode on the gate dielectric layer overlying two edge parts of the gate electrode;
a channel layer on the dielectric layer overlying a center part of the gate electrode;
an insulating capping layer covering the channel layer;
a passivation layer covering the insulating capping layer, the source/drain electrodes, and the gate dielectric layer, wherein the passivation layer has a planar surface;
a via hole through the passivation layer to expose a part of the drain electrode; and
a conductive pattern on the planar surface of the passivation layer to serve as a pixel electrode, wherein the conductive pattern contacts the drain electrode through the via hole,
wherein the channel layer comprises an oxide semiconductor.
2. The thin film transistor as claimed in claim 1 , wherein the insulating capping layer comprises an organic material or an inorganic material.
3. The thin film transistor as claimed in claim 2 , wherein the organic material comprises acrylic series materials.
4. The thin film transistor as claimed in claim 2 , wherein the inorganic material comprises silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, hafnium oxide, or aluminum nitride.
5. The thin film transistor as claimed in claim 1 , wherein a bottom surface of the insulating capping layer and an upper surface of the channel layer have a width difference of 0 μm to 2 μm.
6. The thin film transistor as claimed in claim 1 , wherein the source/drain electrodes comprises copper.