IP Library Granted Patent US 8,890,169
Granted Patent B2
US 8,890,169 · App. 13/883,572 · Granted Nov 18, 2014

Semiconductor device

Inventors: Norifumi Kameshiro (Tokyo, JP); Haruka Shimizu (Kodaira, JP)
Assignee: Hitachi, Ltd.
H01L29/1608H01L29/7811H01L29/0878H01L29/808H01L29/0615H01L29/861H01L29/872H01L29/06H01L29/12H01L29/78H01L29/0843H01L29/6606H01L29/1095H01L29/80H01L29/0692H01L29/8083H01L29/47
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Quick Facts
Patent No.
US 8,890,169
App. No.
13/883,572
Granted
Nov 18, 2014
Kind
B2
Abstract

On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n − -type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.

Claims (36)

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type made of silicon carbide;

a drift layer of the first conductivity type formed on the semiconductor substrate, the drift layer including a first semiconductor region with a first impurity concentration and a second semiconductor region with an impurity concentration higher than the first impurity concentration and in contact with a front surface;

an active region where a current flows at the time of applying a voltage; and

a third semiconductor region of a second conductivity type opposite to the first conductivity type, the third semiconductor region being formed on an outer circumferential part of the active region,

wherein the second semiconductor region extends to the outer circumferential part, and

the third semiconductor region is formed inside the second semiconductor region.

2. The semiconductor device according to claim 1 , further comprising:

a Schottky electrode formed on the active region and making a Schottky contact with the first semiconductor region; and

a fourth semiconductor region of the second conductivity type formed near an edge of the Schottky electrode and in contact with the third semiconductor region,

wherein the fourth semiconductor region is formed inside the second semiconductor region.

3. The semiconductor device according to claim 1 , further comprising:

a group of a plurality of fifth semiconductor regions of the second conductivity type arranged with a predetermined width and a predetermined interval near a front surface of the second semiconductor region of the active region.

4. The semiconductor device according to claim 1 ,

wherein a JFET is formed in the active region, and a source region of the JFET is formed inside the second semiconductor region.

5. The semiconductor device according to claim 1 ,

wherein a MOSFET is formed in the active region, and a source region of the MOSFET is formed inside the second semiconductor region.

6. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type made of silicon carbide;

a drift layer of the first conductivity type with a first impurity concentration formed on the semiconductor substrate;

an active region where a current flows at the time of applying a voltage;

a first semiconductor region of a second conductivity type opposite to the first conductivity type, the first semiconductor region being formed on an outer circumferential part of the active region; and

a second semiconductor region of the first conductivity type with an impurity concentration higher than the first impurity concentration,

wherein an edge of the second semiconductor region located on a side away from the active region is surrounded from its bottom surface to its front surface by the first semiconductor region.

7. The semiconductor device according to claim 6 ,

wherein the second semiconductor region has an edge in a range where the first semiconductor region is formed.

8. The semiconductor device according to claim 6 , further comprising:

a Schottky electrode formed on the active region and making a Schottky contact with the drift layer; and

a third semiconductor region of the second conductivity type formed near an edge of the Schottky electrode and in contact with the first semiconductor region,

wherein the second semiconductor region has an edge in a range where the third semiconductor region is formed.

9. The semiconductor device according to claim 6 ,

wherein the second semiconductor region does not extend to the active region.

10. The semiconductor device according to claim 6 ,

wherein a diode, a JFET, or a MOSFET is formed in the active region.

11. The semiconductor device according to claim 9 ,

wherein a diode, a JFET, or a MOSFET is formed in the active region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2014
From: HITACHI, LTD.
To: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
Reel/Frame 033015/0182 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2013
From: KAMESHIRO, NORIFUMI; SHIMIZU, HARUKA
To: HITACHI, LTD.
Reel/Frame 030499/0657 →
Priority Claims (1)
WO PCT/JP2010/069855 · Nov 8, 2010 · international
Continuity (1)
Related Publication 20130285071A1 · Oct 31, 2013