IP Library › Granted Patent US 8,890,288
Granted Patent B2
US 8,890,288 · App. 13/270,452 · Granted Nov 18, 2014

MOM capacitor having local interconnect metal plates and related method

Inventors: Xiangdong Chen (Irvine, CA); Henry Kuo-Shun Chen (Irvine, CA)
Assignee: Broadcom Corporation
H01L28/86H01L23/5223H01L27/0629
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Quick Facts
Patent No.
US 8,890,288
App. No.
13/270,452
Granted
Nov 18, 2014
Kind
B2
Abstract

According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.

Claims (13)

1. A metal-oxide-metal (MOM) capacitor in a semiconductor die, said MOM capacitor comprising:

a first plurality of capacitor plates and a second plurality of capacitor plates in a MOM capacitor region situated laterally adjacent a transistor region, said first and second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of said semiconductor die;

a local interlayer dielectric between said first plurality of capacitor plates and said second plurality of capacitor plates; and

said first and second plurality of capacitor plates comprised of a local interconnect metal for connecting devices formed in a device layer situated below said first metallization layer, wherein said first and second plurality of capacitor plates do not overlie said transistor region, said first and second plurality of capacitor plates are formed at a same layer as a local interconnect metal body which provides a direct connection to a gate in the transistor region, the gate being formed on a gate dielectric layer, and at least one dielectric layer is disposed below the plurality of capacitor plates and between the local interlayer dielectric and a dielectric layer in which the gate is formed, the dielectric layer in which the gate is formed being separate from the gate dielectric layer.

2. The MOM capacitor of claim 1 , further comprising a first capacitor runner for interconnecting said first plurality of capacitor plates, and a second capacitor runner for interconnecting said second plurality of capacitor plates, said first and second capacitor runners comprising another local interconnect metal for providing connections among said devices formed in said device layer.

3. The MOM capacitor of claim 1 , wherein said first plurality of capacitor plates further comprise a lower local interconnect metal, and said second plurality of capacitor plates further comprise said lower local interconnect metal.

4. The MOM capacitor of claim 3 , further comprising a first capacitor runner for interconnecting said first plurality of capacitor plates, and a second capacitor runner for interconnecting said second plurality of capacitor plates, said first and second capacitor runners comprising another local interconnect metal for providing connections among said devices formed in said device layer.

5. The MOM capacitor of claim 1 , wherein said local interconnect metal comprises a refractory metal.

6. The MOM capacitor of claim 1 , wherein said local interconnect metal comprises copper.

7. The MOM capacitor of claim 1 , wherein said local interlayer dielectric comprises silicon oxide.

8. The MOM capacitor of claim 1 , wherein said local interlayer dielectric comprises silicon nitride.

9. The MOM capacitor of claim 1 , wherein said local interlayer dielectric has a dielectric constant greater than or equal to approximately 3.9 and less than approximately 5.0.

10. The MOM capacitor of claim 1 , wherein said first and second plurality of capacitor plates are situated over an isolation region formed in said device layer.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2011
From: CHEN, XIANGDONG; CHEN, HENRY KUO-SHUN
To: BROADCOM CORPORATION
Reel/Frame 027042/0095 →
Continuity (1)
Related Publication 20130087886A1 · Apr 11, 2013