Method for fabricating semiconductor device

1. A method for fabricating a semiconductor device, the method comprising:

forming a trench in a semiconductor substrate;

forming an insulating layer over a surface of the substrate that defines the trench;

forming a conductive pattern over the insulating layer such that the conducive pattern fills a part of the trench;

removing a portion of the insulating layer from sidewalls of the trench above the conductive pattern;

forming a migration assist layer along the entire surface of the resultant structure that the portion of the insulating layer is removed; and

forming a buried layer in the trench via migrating material from the migration assist layer and the semiconductor substrate.

2. The method of claim 1 , wherein the migration assist layer comprises a silicon layer.

3. The method of claim 1 , wherein the forming of the migration assist layer comprises:

performing an epitaxial growth process.

4. The method of claim 3 , wherein the performing of the epitaxial growth process is performed under a hydrogen (H 2 ) or a nitrogen (N 2 ) atmosphere.

5. The method of claim 1 , wherein removing the portion of the insulating layer comprises:

etching the portion of the insulating layer.

6. The method of claim 1 , further comprising:

forming a defect prevention layer over the conductive pattern, before the portion of the insulating layer is removed.

7. The method of claim 6 , wherein the defect prevention layer comprises a polysilicon layer.

8. The method of claim 1 , wherein the semiconductor substrate comprises a silicon substrate.

9. The method of claim 8 , wherein the migrating material from the migration assist layer and the semiconductor substrate to form the buried layer comprises

migrating material from the migration assist layer and the semiconductor substrate using a thermal process performed in a hydrogen (H 2 ) or a nitrogen (N 2 ) atmosphere.

10. The method of claim 1 , wherein the conductive pattern comprises a metal layer.

11. A method for fabricating a semiconductor device, the method comprising:

forming a trench in a silicon substrate;

forming an insulating layer on a surface of the substrate that defines the trench;

forming a bit line over the insulating layer such that the bit line partially fills a part of the trench;

forming a first silicon-containing layer over the bit line;

removing a portion of the insulating layer from sidewalls of the trench above the first silicon-containing layer;

forming a second silicon-containing layer along the entire surface of the resultant structure that the portion of the insulating layer is removed;

forming, in the trench, a third silicon-containing layer via migrating material from the second silicon-containing layer and the substrate;

forming a body line having the bit line buried therein by etching the second silicon-containing layer and the silicon substrate; and

etching the body line to form a pillar including a channel area of a vertical channel transistor.

12. The method of claim 11 , wherein the first silicon-containing layer comprises a polysilicon layer.

13. The method of claim 11 , wherein the second silicon-containing layer and the third silicon-containing layer comprise single crystalline silicon layers.

14. The method of claim 11 , wherein the forming of the second silicon-containing layer comprises:

performing an epitaxial growth process.

15. The method of claim 14 , wherein the performing of the epitaxial growth process is performed under a hydrogen (H 2 ) or a nitrogen (N 2 ) atmosphere.

16. The method of claim 11 , wherein removing the portion of the insulating layer comprises:

etching the portion of the insulating layer.

17. The method of claim 11 , wherein the migrating material from the second silicon-containing layer and the substrate comprises:

migrating material from the second silicon-containing layer and the substrate using a thermal process performed in a hydrogen (H 2 ) or a nitrogen (N 2 ) atmosphere.

18. The method of claim 11 , further comprising:

forming, before the forming of the body line, a fourth silicon-containing layer over the third silicon-containing layer and over the silicon substrate.

19. The method of claim 18 , wherein the fourth silicon-containing layer comprises single crystalline silicon layer.

20. The method of claim 11 , wherein the bit line comprises a conductive layer.