Top gate thin film transistor with independent field control for off-current suppression
A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region.
1. A method for forming a bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression, the method comprising:
providing a substrate;
forming source and drain regions overlying the substrate, each having a channel interface top surface;
forming a channel interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively;
forming a first dielectric layer overlying the source, drain, and channel;
forming a first gate overlying the first dielectric, having a drain sidewall located between the contact regions;
forming a second dielectric layer overlying the first gate and first dielectric; and,
forming a second gate overlying the second dielectric and located over the drain contact region.
2. The method of claim 1 wherein forming the first gate includes locating the first gate over the source contact region.
3. The method of claim 1 wherein forming the S/D regions includes forming a drain region having a channel interface edge; and,
wherein forming the first gate includes locating the first gate drain sidewall over the channel, in a range of 0 to 7500 Å from the drain channel interface edge.
4. The method of claim 1 wherein forming the first dielectric layer and second dielectric layer includes forming each layer from a material selected from a group consisting of silicon nitride, silicon dioxide, and organic dielectrics.
5. The method of claim 1 wherein forming the first and second dielectric layers includes forming the first and second dielectric layers from different materials.
6. The method of claim 1 wherein forming the first dielectric layer includes forming a first dielectric layer having a thickness of 1000 Å, or less.
7. The method of claim 1 wherein forming the first dielectric layer includes forming a first dielectric layer having an interfacial defect density adjacent the channel not exceeding 1×10 12 (cm 2 eV) −1 .
8. The method of claim 1 wherein forming the source and drain regions includes forming source and drain regions from a first material; and,
wherein forming the channel includes forming the channel from a second material different than the first material.
9. The method of claim 1 wherein forming the source and drain regions includes forming the source and drain from a material selected from the group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors; and,
wherein forming the channel region includes forming the channel region from a material selected from a group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors.
10. A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression, the TG TFT comprising:
a substrate;
source and drain regions overlying the substrate, each having a channel interface top surface;
a channel interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively;
a first dielectric layer overlying the source, drain, and channel;
a first gate overlying the first dielectric, having a drain sidewall located between the contact regions;
a second dielectric layer overlying the first gate and first dielectric; and,
a second gate overlying the second dielectric and located over the drain contact region.
11. The TG TFT of claim 10 wherein the first gate is located over the source contact region.
12. The TG TFT of claim 10 wherein the drain region has a channel interface edge; and,
wherein the first gate drain sidewall is located over the channel, in a range of 0 to 7500 Å from the drain channel interface edge.
13. The TG TFT of claim 10 wherein the first dielectric layer and second dielectric layer are each a material selected from a group consisting of silicon nitride, silicon dioxide, and organic dielectrics.
14. The TG TFT of claim 10 wherein the first and second dielectric layers are different materials.
15. The TG TFT of claim 10 wherein the first dielectric layer has a thickness of 1000 Å, or less.
16. The TG TFT of claim 10 wherein the first dielectric layer has an interfacial defect density adjacent the channel not exceeding 1×10 12 (cm 2 eV) −1 .
17. The TG TFT of claim 10 wherein the source and drain regions are a first material; and,
wherein the channel is a second material different than the first material.
18. The TG TFT of claim 10 wherein the source and drain regions are a material selected from the group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors; and,
wherein the channel is a material selected from a group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors.