IP Library Granted Patent US 8,901,552
Granted Patent B2
US 8,901,552 · App. 13/226,713 · Granted Dec 2, 2014

Top gate thin film transistor with multiple oxide semiconductor layers

Inventors: Shunpei Yamazaki (Setagaya, JP); Yusuke Nonaka (Atsugi, JP); Takayuki Inoue (Isehara, JP); Masashi Tsubuku (Atsugi, JP); Kengo Akimoto (Atsugi, JP); Akiharu Miyanaga (Tochigi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L21/02488H01L21/02565H01L21/02554
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,901,552
App. No.
13/226,713
Granted
Dec 2, 2014
Kind
B2
Abstract

An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al 2 O 3 , α-Ga 2 O 3 , In 2 O 3 , Ti 2 O 3 , V 2 O 3 , Cr 2 O 3 , or α-Fe 2 O 3 ) is used.

Claims (39)

1. A semiconductor device comprising:

a first material film having a hexagonal crystal structure over an insulating surface;

a second material film having a hexagonal crystal structure on and in contact with the first material film;

a gate insulating layer over the second material film;

an insulating layer over the gate insulating layer, the insulating layer comprising an opening portion; and

a gate electrode layer over the insulating layer, the gate electrode layer being in contact with the gate insulating layer through the opening portion;

wherein the second material film is thicker than the first material film.

2. The semiconductor device according to claim 1 , wherein the first material film comprises gallium oxide or aluminum oxide.

3. The semiconductor device according to claim 1 , wherein the first material film comprises α-Al 2 O 3 , α-Ga 2 O 3 , In 2 O 3 , Ti 2 O 3 , V 2 O 3 , Cr 2 O 3 , or α-Fe 2 O 3 .

4. The semiconductor device according to claim 1 , wherein the second material film comprises zinc, indium, or gallium.

5. The semiconductor device according to claim 1 , further comprising an n+ layer over the second material film, a source electrode and a drain electrode over the n+ layer.

6. The semiconductor device according to claim 1 , further comprising an insulating layer over the gate electrode layer.

7. The semiconductor device according to claim 1 , wherein the gate insulating layer comprises silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, or aluminum nitride oxide.

8. A semiconductor device comprising:

a first insulating layer over a substrate;

an oxide semiconductor layer over the first insulating layer;

a second insulating layer over the oxide semiconductor layer;

a third insulating layer over the second insulating layer, the third insulating layer comprising an opening portion; and

a gate electrode layer over the third insulating layer, the gate electrode layer being in contact with the second insulating layer through the opening portion,

wherein the first insulating layer has a corundum crystal structure.

9. The semiconductor device according to claim 5 , wherein the n+ layer comprises indium oxide, indium zinc oxide, tin oxide, or indium tin oxide.

10. The semiconductor device according to claim 8 , further comprising an n+ layer over the oxide semiconductor layer, a source electrode and a drain electrode over the n+ layer.

11. The semiconductor device according to claim 8 , wherein the first insulating layer comprises aluminum nitride or aluminum oxide.

12. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises zinc, indium, or gallium.

13. The semiconductor device according to claim 8 , further comprising an insulating layer over the gate electrode layer.

14. The semiconductor device according to claim 10 , wherein the n+ layer comprises indium oxide, indium zinc oxide, tin oxide, or indium tin oxide.

15. The semiconductor device according to claim 8 , wherein the second insulating layer comprises silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, or aluminum nitride oxide.

16. A semiconductor device comprising:

a first oxide semiconductor layer over a substrate;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a first insulating layer over the third oxide semiconductor layer;

a second insulating layer over the first insulating layer, the second insulating layer comprising an opening portion; and

a gate electrode layer over the second insulating layer, the gate electrode layer being in contact with the first insulating layer through the opening portion,

wherein the first oxide semiconductor layer has a corundum crystal structure.

17. The semiconductor device according to claim 16 , wherein the first oxide semiconductor layer comprises gallium oxide.

18. The semiconductor device according to claim 16 , wherein the second oxide semiconductor layer comprises zinc, indium, or gallium.

19. The semiconductor device according to claim 16 , further comprising a source electrode and a drain electrode over the third oxide semiconductor layer.

20. The semiconductor device according to claim 16 , wherein the third oxide semiconductor layer comprises indium oxide, indium zinc oxide, tin oxide, or indium tin oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2011
From: YAMAZAKI, SHUNPEI; NONAKA, YUSUKE; INOUE, TAKAYUKI; TSUBUKU, MASASHI; AKIMOTO, KENGO; MIYANAGA, AKIHARU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 026864/0947 →
Priority Claims (1)
JP 2010-204968 · Sep 13, 2010 · national
Continuity (1)
Related Publication 20120061663A1 · Mar 15, 2012