Semiconductor device and structure for heat removal
View Patent ↗A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.
1. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal interconnection layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm,
wherein said second transistors are interconnected to form logic circuits, and
wherein said second layer comprises a thermally conductive shallow trench isolation (STI).
2. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal interconnection layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm, and
wherein said second transistors are interconnected to form logic circuits,
a second metal interconnection layer overlaying said second transistors; and
an isolation layer disposed between said second transistors and said second metal interconnection layer,
wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.
3. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm,
wherein said second transistors are interconnected to form at least one NAND gate, and
wherein said second layer comprises a thermally conductive shallow trench isolation (STI).
4. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm, and
wherein said second transistors are interconnected to form at least one NAND gate,
a second metal interconnection layer overlaying said second transistors; and
an isolation layer disposed between said second transistors and said second metal interconnection layer,
wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.
5. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm,
wherein said second transistors are interconnected to form at least one transmission gate, and
wherein said second layer comprises a thermally conductive shallow trench isolation (STI).
6. A device, comprising:
an integrated circuit chip, wherein said integrated circuit chip comprises:
a first layer comprising a plurality of first transistors;
a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;
a second layer comprising second transistors comprising a mono-crystal channel;
wherein said second layer has a thickness of less than 200 nm, and
wherein said second transistors are interconnected to form at least one transmission gate,
a second metal interconnection layer overlaying said second transistors; and
an isolation layer disposed between said second transistors and said second metal interconnection layer,
wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.