IP Library › Granted Patent US 8,901,635
Granted Patent B2
US 8,901,635 · App. 13/414,988 · Granted Dec 2, 2014

Semiconductor memory device and method for manufacturing the same

Inventors: Jun Fujiki (Kanagawa-ken, JP); Yoshiaki Fukuzumi (Kanagawa-ken, JP); Hideaki Aochi (Kanagawa-ken, JP); Tomoko Fujiwara (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/7926H01L27/11582H01L29/66833
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Quick Facts
Patent No.
US 8,901,635
App. No.
13/414,988
Granted
Dec 2, 2014
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

Claims (15)

1. A semiconductor memory device, comprising:

a stacked body including a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films;

a semiconductor pillar piercing the stacked body;

an insulating film provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed;

a charge storage film provided between the insulating film and the electrode films; and

a support portion provided on a lower end side of the semiconductor pillar and configured to maintain a distance between the insulating film and the semiconductor pillar,

the semiconductor pillar including germanium,

an upper end portion of the semiconductor pillar being supported by an interconnect provided above the stacked body, and

the support portion including aluminum.

2. The device according to claim 1 , wherein an upper end of the support portion is lower than a lower end of the electrode film of a lowermost layer.

3. The device according to claim 1 , wherein the insulating film and the gap are used as a tunneling insulating film.

4. The device according to claim 1 , comprising a blocking insulating film including aluminum oxide provided between the charge storage film and the electrode films.

5. The device according to claim 1 , wherein:

the semiconductor pillar is multiply provided; and

the device comprises a connection member connecting lower end portions of mutually-adjacent semiconductor pillars.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2012
From: FUJIKI, JUN; FUKUZUMI, YOSHIAKI; AOCHI, HIDEAKI; FUJIWARA, TOMOKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 027828/0475 →
Priority Claims (2)
JP 2011-198806 · Sep 12, 2011 · national
JP 2011-207058 · Sep 22, 2011 · national
Continuity (1)
Related Publication 20130062681A1 · Mar 14, 2013