Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.
1. A semiconductor memory device comprising:
memory cell arrays each comprising blocks, the block being unit of erase and comprising a plurality of string-groups, each string-group comprising strings, each string comprising a first transistor, memory cell transistors, a second transistor coupled in series, the first transistor being connected to different bit line and the second transistor being connected to same source line,
wherein
the memory cell arrays are provided with different respective block address signals,
the memory cell arrays are provided with different respective string address signals,
each of the block address signals specifies one block,
each of the string address signals specifies one string-group,
a first string group of a first one of the memory cell arrays and a second string group of a second one of the memory cell arrays are accessible in parallel, and
an address of the first string group and an address of the second string group are specified separately.
2. The device of claim 1 , further comprising a first driver set for each memory cell array, and wherein the first driver set:
receives a string address signal; and
drives a first line selectively coupled to a gate of a first transistor of a string-group specified by the string address signal, and drives a second line selectively coupled to a gate of a second transistor of the specified string.
3. The device of claim 2 , wherein:
the first driver sets comprises first driver pairs, each first driver pair being provided for each corresponding string-groups; and
each first driver pair is coupled to a first line selectively coupled to a gate of a first transistor of a corresponding string-group, and coupled to a second line selectively coupled to a gate of a second transistor of the corresponding string.
4. The device of claim 3 , wherein one first driver pair corresponding to one string-group specified by the string address signal drives corresponding first and second lines.
5. The device of claim 4 , wherein first driver sets corresponding to respective string-groups other than the specified string do not operate.
6. The device of claim 5 , wherein:
the device further comprises decoders, the decoders being provided for each memory cell array;
the decoders receive a corresponding block address signal; and
one decoder for one block specified by the block address signal couples one first driver pair corresponding to each of string-groups of the specified block to a gate of a first transistor and a gate of a second transistor of a corresponding string-group, respectively.
7. The device of claim 6 , further comprising second drivers which output voltages applied to respective gates of the memory cell transistors.
8. The device of claim 7 , wherein one decoder for the specified block couples respective outputs of the second drivers to respective gates of memory cell transistors of each of string-groups of the specified block.
9. The device of claim 8 , wherein the second drivers are selectively coupled to respective gates of memory cell transistors of each of the memory cell arrays, respectively.
10. The device of claim 1 , further comprising a controller which outputs the block address signals and the string address signals.
11. The device of claim 1 , wherein, in one block, memory cell transistors of respective string-groups share a word line.
12. The device of claim 1 , wherein:
the first and second memory cell arrays are accessed in parallel; and
one string-group of the first memory cell array and one string-group of the second memory cell array make a set.
13. The device of claim 12 , wherein one good string-group of one block including a defective string-group of the first memory cell array and one string of the second memory cell array make a set.
14. The device of claim 13 , wherein one block which includes no defective string-group of the first memory cell array and one block which includes no defective string-group of the second memory cell array make a set.
15. The device of claim 14 , wherein a string-group or block which does not make a set of the first memory cell array stores management data.
16. The device of claim 12 , further comprising a controller which accesses string-groups which make a set in parallel.
17. The device of claim 12 , wherein:
a third one of the memory cell arrays is accessed in parallel with the first and second memory cell arrays; and
one string-group of the first memory cell array, one string-group of the second memory cell array, and one string-group of the third memory cell array make a set.