Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

1. A method for calculating at least one multiply-sum of two carry-less multiplications of two input operands, the method comprising:

using input data busses for said input operands and an output data bus for an overall calculation result, each bus comprising a width of 2n bits, where n is an integer greater than one;

calculating, via multiplier circuitry, said carry-less multiplications of said two input operands for a lower level of a hierarchical structure;

calculating said at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the hierarchical structure based on said carry-less multiplications of the lower level;

in a top level of said hierarchical structure, calculating and outputting a first multiply-sum of two carry-less multiplications of two input operands each comprising a width of n bits by using a bit-wise exclusive OR function;

in a first mode of operation, outputting said first multiply-sum as overall calculation result, and in an at least one further mode of operation:

calculating 2 k intermediate multiply-sums of two carry-less multiplications of two input operands each comprising a width of n/2 k bits, with k=1, 2, . . . , depending on said further mode of operation, by using exclusive OR functions in sub-levels of said hierarchical structure for summing said multiplications; and

outputting said 2 k intermediate multiply-sum results as said overall calculation result.

2. The method according to claim 1 , comprising:

using full bit width of said carry-less multiplications of said lower level for calculating said at least one multiply-sum result of said higher level, and

using half of said bit width of said carry-less multiplications of said lower level for calculating said at least one intermediate multiply-sum of said higher level.

3. The method according to claim 1 , comprising, in a bottom level of said hierarchical structure, calculating and outputting carry-less basic multiplication of two input operands each comprising a certain basic width of m bits, where m is greater than 1, n/m=2 j , and j=0, 1, 2, . . . .

4. A data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, comprising:

multiplier circuitry;

input data busses to said multiplier circuitry for said input operands, each bus comprising a width of 2n bits, where n is an integer greater than one;

a hierarchical structure comprising:

a lower level for calculating said carry-less multiplications of said two input operands, and

a higher level for calculating said at least one multiply-sum and at least one intermediate multiply-sum based on said carry-less multiplications of the lower level; and

an output data bus for outputting a certain number of multiply-sum results as an overall calculation result depending on mode of operation using the full width 2n of said output data bus; and wherein sub levels of said hierarchical structure comprise:

components for calculating 2 k intermediate multiply-sum results of two carry-less multiplications of two input operands each comprising a width of n/2 k bits, with k=1, 2, . . . , depending on said mode of operation, and

exclusive OR function gates for bit-wise summing and outputting said multiplication results.

5. The data processing unit according to claim 4 , wherein said hierarchical structure is adapted to use:

the full bit width of said carry-less multiplication results of said lower level for calculating said at least one multiply-sum result of said higher level, and

half of said bit width of said carry-less multiplication results of said level lower for calculating said at least one intermediate multiply-sum result of said higher level.

6. The data processing unit according to claim 4 , wherein a top level of said hierarchical structure comprises an exclusive OR function gate that bit-wise calculates a first multiply-sum result of two carry-less multiplications of two input operands each comprising a width of n bits.

7. The data processing unit according to claim 4 , wherein a bottom level of said hierarchical structure comprises at least one basic multiplier that calculates and outputs carry-less basic multiplication results of two input operands each comprising a certain basic width of m bits, with m=2, 3, . . . , n/m=2 j , and j=0, 1, 2, . . . .

8. The data processing unit according to claim 4 , wherein at least one multiplexer for outputting said first multiply-sum as an overall calculation result in a first mode of operation, and for outputting said 2 k intermediate multiply-sum results as said overall calculation result in at least one further mode of operation.

9. The data processing unit according to claim 4 , wherein said hierarchical structure is implemented as Karatsuba-Ofman structure.

10. The data processing unit according to claim 9 , wherein exclusive OR function gates used in sub levels of said structure to calculate said carry-less multiplication results are also used for calculating said 2 k intermediate multiply-sum results.

11. A computer program product for calculating at least one multiply-sum of two carry-less multiplications of two input operands, the computer program product comprising:

a non-transitory computer readable medium:

first program instructions to calculate said carry-less multiplications of said two input operands for a lower level of a hierarchical structure; and

second program instructions to calculate said at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the hierarchical structure based on said carry-less multiplications of the lower level;

wherein, in a bottom level of said hierarchical structure, third program instructions calculate and output carry-less basic multiplication of two input operands each comprising a certain basic width of m bits, where m is greater than 1, n/m=2 j , and j=0, 1, 2, . . . ; and

in a first mode of operation, fourth program instructions output said first multiply-sum as overall calculation result, and in an at least one further mode of operation, fifth program instructions:

calculate 2 k intermediate multiply-sums of two carry-less multiplications of two input operands each comprising a width of n/2 k bits, with k=1, 2, . . . , depending on said further mode of operation, by using exclusive OR functions in sub-levels of said hierarchical structure for summing said multiplications, and

output said 2 k intermediate multiply-sum results as said overall calculation result; and

wherein said first second, third, fourth and fifth program instructions are stored on said computer readable medium.

12. The computer program product according to claim 11 , wherein the second program instructions:

use full bit width of said carry-less multiplications of said lower level for calculating said at least one multiply-sum result of said higher level, and

use half of said bit width of said carry-less multiplications of said lower level for calculating said at least one intermediate multiply-sum of said higher level.

13. The computer program product according to claim 11 , wherein, in a top level of said hierarchical structure, sixth program instructions calculate and output a first multiply-sum of two carry-less multiplications of two input operands each comprising a width of n bits by using a bit-wise exclusive OR function.