Transistor having impurity distribution controlled substrate and method of manufacturing the same
A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
1. A semiconductor device comprising:
a semiconductor substrate;
a buried insulating layer formed on the semiconductor substrate;
a semiconductor layer formed on the buried insulating layer, the semiconductor layer includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion;
a gate insulating film formed on a sidewall surface of the narrow portion; and
a gate electrode formed on the gate insulating film,
wherein an impurity concentration of the semiconductor substrate directly below the narrow portion is higher than an impurity concentration of the narrow portion, and
the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than an impurity concentration of the semiconductor substrate directly below the two wide portions.
2. The device according to claim 1 , wherein the impurity concentration of the semiconductor substrate directly below the narrow portion is 1E18 cm −3 or more and 1E21 cm −3 or less.
3. The device according to claim 1 , wherein a film thickness of the buried insulating layer is 3 nm or more and 25 nm or less.
4. The device according to claim 1 , wherein the gate insulating film is formed on an upper surface of the narrow portion.
5. The device according to claim 1 , wherein the impurity concentration of the narrow portion and the impurity concentration of the semiconductor substrate directly below the two wide portions are lower than the impurity concentration of the semiconductor substrate directly below the narrow portion by one order of magnitude or more.
6. The device according to claim 1 , wherein the impurity concentration of the narrow portion is 5E15 cm −3 or more and 1E18 cm −3 or less.
7. The device according to claim 1 , wherein the impurity concentration of the semiconductor substrate directly below the narrow portion is 5E15cm −3 or more and 1E18 cm −3 or less.
8. The device according to claim 1 , wherein a height of the narrow portion is 25 nm or less.
9. The semiconductor device according to claim 1 , wherein the semiconductor substrate and the semiconductor layer are made of silicon.
10. The semiconductor device according to claim 1 , wherein the gate insulating film is silicon oxide film.