Array substrate and method of fabricating the same
An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.
1. An array substrate comprising:
a gate electrode;
a gate insulating layer on the gate electrode;
an oxide semiconductor layer on the gate insulating layer, exposing two sides of the gate insulating layer;
an etch stopper on the oxide semiconductor layer and entirely over the substrate, the etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer;
a source electrode, a drain electrode and a pixel electrode on the etch stopper, wherein the source and drain electrodes are spaced apart from each other with the oxide semiconductor layer therebetween, wherein the pixel electrode is connected to the drain electrode;
a first passivation layer on the source and drain electrodes and the pixel electrode and entirely over the substrate, the first passivation layer including a second contact hole which fully overlaps the first contact hole, has an area greater than the first contact hole, the second contact hole exposes each of both ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and
a connection pattern contacting both the oxide semiconductor layer and the source and drain electrodes respectively.
2. The substrate according to claim 1 , further comprising:
a second passivation layer on the connection pattern and entirely over the substrate; and
a common electrode on the second passivation layer and having bar-shaped openings in the area over the pixel electrode.
3. The substrate according to claim 1 , wherein the source and drain electrodes each include a lower layer made of transparent conductive material, and an upper layer made of metal material.
4. The substrate according to claim 3 , wherein the pixel electrode extends the drain electrode, from the lower layer of the drain electrode.
5. The substrate according to claim 1 , wherein the gate insulating layer, the gate electrode is patterned together and have the same plane shape.
6. The substrate according to claim 1 , further comprising a gate pad electrode, wherein a gate pad contact hole extends through the gate insulating layer, the etch stopper, the first passivation layer and the second passivation layer above the gate pad electrode, a gate auxiliary pad electrode is located at least in the gate pad contact hole and contacts the gate pad electrode.