Flash memory apparatus with serial interface and reset method thereof
A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.
1. A flash memory apparatus with a serial interface, comprising:
a selector, coupled to one of a write protect pin or a hold pin of the flash memory apparatus, for deciding whether or not to connect the write protect pin or the hold pin to a reset signal line according to a selecting signal;
a core circuit, coupled to the reset signal line, for receiving a reset signal transmitted by the reset signal line to activate a reset operation; and
a programmable data bank, coupled to the selector, wherein a selecting data is written into the programmable data bank through a programming method, and the programmable data bank outputs the selecting data to serve as the selecting signal.
2. The flash memory apparatus as claimed in claim 1 , wherein when the selector cuts off a connection between the write protect pin and the reset signal line according to the selecting signal, the selector connects the write protect pin to a write protect signal line, wherein the write protect signal line is connected to the core circuit for transmitting a write protect signal to the core circuit.
3. The flash memory apparatus as claimed in claim 1 , wherein when the selector cuts off a connection between the hold pin to the reset signal line according to the selecting signal, the selector connects the hold pin to a hold signal line, wherein the hold signal line is connected to the core circuit for transmitting a hold signal to the core circuit.
4. The flash memory apparatus as claimed in claim 1 , wherein the programmable data bank is a non-volatile memory.
5. The flash memory apparatus as claimed in claim 1 , wherein the programmable data bank comprises:
a register, coupled to the selector for storing the selecting data, and outputting the selecting data to serve as the selecting signal.
6. The flash memory apparatus as claimed in claim 1 , wherein the serial interface is a serial peripheral interface (SPI).
7. The flash memory apparatus as claimed in claim 1 , further comprising:
an input buffer, coupled to the selector, and directly connected to the write protect pin and the hold pin.
8. A method for activating a reset operation of a flash memory apparatus with a serial interface, comprising:
receiving a selecting data by a programmable data bank through a programming method, wherein the selecting data is outputted to serve as a selecting signal by the programmable data bank;
deciding whether or not to connect a write protect pin or a hold pin of the flash memory apparatus to a reset signal line according to the selecting signal; and
making a core circuit of the flash memory apparatus to activate the reset operation through the write protect pin or the hold pin connected to the reset signal line, wherein the reset signal transmitted by the reset signal line is received by the core circuit to activate the reset operation.