IP Library › Granted Patent US 8,916,921
Granted Patent B2
US 8,916,921 · App. 12/705,088 · Granted Dec 23, 2014

Non-volatile semiconductor storage device including a dielectric with low permittivity in memory cells arranged in a three dimensional manner

Inventors: Hiroyasu Tanaka (Tokyo, JP); Hideaki Aochi (Kawasaki, JP); Ryota Katsumata (Yokohama, JP); Masaru Kidoh (Komae, JP); Masaru Kito (Yokohama, JP); Yoshiaki Fukuzumi (Yokohama, JP); Yosuke Komori (Yokohama, JP); Megumi Ishiduki (Yokohama, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11578H01L27/11582G11C16/0483
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,916,921
App. No.
12/705,088
Granted
Dec 23, 2014
Kind
B2
Abstract

A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness D EOT that satisfies the following relation (1). D sio2 <D EOT <D k   (1) D sio2 denotes a thickness of the dielectric when the dielectric is composed of silicon oxide with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers. D k denotes such an equivalent oxide thickness of a first dielectric that provides the resistance value Rsio2. The resistance value Rsio2 being defined as a resistance value of the first semiconductor layer for each of the first conductive layers when the dielectric is composed of silicon oxide and has a film thickness of D sio2 .

Claims (35)

1. A non-volatile semiconductor storage device comprising:

a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series,

each of the memory strings comprising:

a first semiconductor layer having a columnar portion extending in a vertical direction with respect to a substrate;

an electric charge accumulation layer surrounding a side surface of the first semiconductor layer; and

a plurality of first conductive layers surrounding a side surface of the electric charge accumulation layer and functioning as control electrodes of the memory cells,

the plurality of first conductive layers being provided at a certain interval L in the vertical direction, with a dielectric sandwiched therebetween,

the dielectric including a first dielectric with a lower dielectric constant than that of silicon oxide,

the certain interval L being set so that the first dielectric has an equivalent oxide thickness D EOT that satisfies the following relation (1), wherein the equivalent oxide thickness D EOT is defined as EOT=T×(∈ ox /∈ x ), in which T is a physical thickness of the first dielectric, ∈ ox is the dielectric constant of silicon oxide, and ∈ x is the dielectric constant of the first dielectric:

D sio2 <D EOT <D k   (1)

in which D sio2 denotes an equivalent oxide thickness of the first dielectric with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers, and,

R sio2 defines a resistance value of an entire part of the first semiconductor layer that is adjacent in a direction parallel to the substrate to one of the first conductive layers, and that has an extent between top and bottom surfaces of the one of the first conductive layers, if the first dielectric was composed of silicon oxide having a film thickness of D sio2 , and

D k denotes an equivalent oxide thickness of the first dielectric when the first dielectric provides the resistance value R sio2 in the part of the first semiconductor layer.

2. The non-volatile semiconductor storage device according to claim 1 , wherein

the first dielectric comprises vacuum or gas with a lower dielectric constant than that of silicon oxide.

3. The non-volatile semiconductor storage device according to claim 1 , wherein

the first dielectric comprises an interlayer insulation layer with a lower dielectric constant than that of silicon oxide.

4. The non-volatile semiconductor storage device according to claim 1 , wherein

each of the memory strings comprises:

a first insulation layer formed between the electric charge accumulation layer and the first semiconductor layer; and

a second insulation layer formed between the electric charge accumulation layer and the first conductive layers, and

the second insulation layer has a higher dielectric constant than that of silicon oxide.

5. The non-volatile semiconductor storage device according to claim 4 , wherein

the second insulation layer comprises aluminum oxide.

6. The non-volatile semiconductor storage device according to claim 1 , further comprising:

a selection transistor connected to one end of a respective one of the memory strings and controlling conduction of the memory strings,

wherein the selection transistor comprises:

a second semiconductor layer extending in the vertical direction from a top or bottom surface of the first semiconductor layer;

a third insulation layer surrounding a side surface of the second semiconductor layer; and

a second conductive layer surrounding a side surface of the third insulation layer, and

the third insulation layer has a higher dielectric constant than that of silicon oxide.

7. The non-volatile semiconductor storage device according to claim 6 , wherein

the third insulation layer comprises aluminum oxide.

8. The non-volatile semiconductor storage device according to claim 1 , wherein

the first conductive layers are formed in a stripe pattern at a certain pitch in a first direction parallel to the substrate.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2010
From: TANAKA, HIROYASU; AOCHI, HIDEAKI; KATSUMATA, RYOTA; KIDOH, MASARU; KITO, MASARU; FUKUZUMI, YOSHIAKI; KOMORI, YOSUKE; ISHIDUKI, MEGUMI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023940/0146 →
Priority Claims (1)
JP 2009-032697 · Feb 16, 2009 · national
Continuity (1)
Related Publication 20100207193A1 · Aug 19, 2010