Body voltage sensing based short pulse reading circuit
As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.
1. A body voltage based sense circuit (BVSC) apparatus for short pulse reading (SPR) of a memory, said apparatus comprising:
a body voltage sensing data circuit configured to sense resistance of a memory cell that has two states, said body voltage sensing data circuit having a voltage output in response to short pulse reading (SPR) of said memory cell;
said body voltage sensing data circuit configured to translate the states of the memory cell into a sense data voltage signal;
a body voltage sensing reference circuit configured to generate a sense reference voltage signal;
a second stage sense amplifier configured to compare said sense data voltage signal and said sense reference voltage signal and output a data signal; and
a capturing latch circuit configured to capture said data signal using positive feedback;
wherein said captured data signal digitally represents the state of said memory cell as a binary output; and
wherein said body voltage sensing is performed on a body-connected load that provides a high sensing margin (SM) in which body and drain terminals of a transistor of said body voltage sensing data circuit are coupled together.
2. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit, said body voltage sensing reference circuit, and said second stage sense amplifier are configured for activation in response to receiving a sensing activation signal from memory control logic.
3. The apparatus recited in claim 2 , wherein said capturing latch is configured for activation in response to receiving a latching activation signal from memory control logic.
4. The apparatus recited in claim 3 , wherein sensing is enabled in response to receiving a sensing activation signal from memory control logic for a sensing time before receiving a latching activation signal from memory control logic, after which said data signal is output from said capturing latch as said binary output.
5. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit is configured for coupling to a memory cell in which memory state is retained by one or more magnetic tunnel junctions (MTJs).
6. The apparatus recited in claim 1 , wherein each said memory cell comprises a magnetic tunnel junction (MTJ).
7. The apparatus recited in claim 6 , wherein each magnetic tunnel junction (MTJ) comprises two ferromagnetic layers separated by a thin nonconductive tunneling barrier, and exhibit two resistive states determined by relative magnetization directions of the two ferromagnetic layers, with a parallel (P) orientation producing a low resistance (R P ) and an anti-parallel (AP) orientation producing a high resistance (R AP ).
8. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit is configured for operation within a spin-torque transfer random access memory (STT-RAM).
9. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit generates a sensing current during a read pulse that approximates current magnitude utilized when writing to said memory cell with a write pulse having a write pulse width, yet width of said read pulse is less than or equal to one-tenth of said write pulse width.
10. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit provides a sensing margin on the order of 700 mV when utilizing a supply voltage under 1 Volt.
11. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit provides a 200 mV sensing margin at a sensing time of approximately 0.67 ns for 65 nm device geometry.
12. The apparatus recited in claim 1 , wherein said body voltage sensing data circuit utilizes shorter current pulses for reading which increase read speed, while reducing read disturbance probability.
13. A body voltage based sense circuit (BVSC) apparatus for short pulse reading (SPR) of a memory, said apparatus comprising:
a body voltage sensing data circuit for sensing resistance of a magnetic tunnel junction memory cell having two states, said body voltage sensing data circuit having a voltage output in response to short pulse reading (SPR) of said memory cell;
said body voltage sensing data circuit configured to translate the states of the magnetic tunnel junction memory cell into a sense data voltage signal;
a body voltage sensing reference circuit for sensing resistance of a reference magnetic tunnel junction memory cell and translating this into a sense reference voltage signal;
a second stage sense amplifier configured to compare said sense data voltage signal and said sense reference voltage signal and output a data signal; and
a capturing latch configured for capturing said data signal, as a captured data signal, using positive feedback;
wherein said captured data signal digitally represents the state of said memory cell as a binary output; and
wherein said body voltage sensing is performed on a body-connected load that provides a high sensing margin (SM) in which body and drain terminals of a transistor of said body voltage sensing data circuit are coupled together.
14. The apparatus recited in claim 13 , wherein said body voltage sensing data circuit, said body voltage sensing reference circuit, and said second stage sense amplifier are configured for activation in response to receiving a sensing activation signal from memory control logic.
15. The apparatus recited in claim 14 , wherein said capturing latch is configured for activation in response to receiving a latching activation signal from memory control logic.
16. The apparatus recited in claim 15 , wherein sensing is enabled in response to receiving a sensing activation signal from memory control logic for a sensing time before receiving a latching activation signal from memory control logic, after which said data signal is output from said capturing latch as said binary output.
17. The apparatus recited in claim 13 , wherein each magnetic tunnel junction (MTJ) comprises two ferromagnetic layers separated by a thin nonconductive tunneling barrier, and exhibits two resistive states determined by relative magnetization directions of ferromagnetic layers, with a parallel (P) orientation producing a low resistance (R P ) and an anti-parallel (AP) orientation producing a high resistance (R AP ).
18. The apparatus recited in claim 13 , wherein said body voltage sensing data circuit is configured for operation within a spin-torque transfer random access memory (STT-RAM).
19. The apparatus recited in claim 13 , wherein said body voltage sensing data circuit generates a sensing current during a read pulse that approximates current magnitude utilized when writing to said memory cell with a write pulse having a write pulse width, yet width of said read pulse is less than or equal to one-tenth of said write pulse width.
20. A body voltage based sense circuit (BVSC) apparatus for short pulse reading (SPR) of a spin-torque transfer random access memory (STT-RAM), said apparatus comprising:
a body voltage sensing data circuit for sensing configured to sense resistance of a magnetic tunnel junction (MTJ) memory cell that has two states, said body voltage sensing data circuit having a voltage output in response to short pulse reading (SPR) of said MTJ memory cell;
said body voltage sensing data circuit configured to translate the states of the MTJ memory cell into a sense data voltage signal;
a body voltage sensing reference circuit for averaging high and low values of sensed voltage for a magnetic tunnel junction (MTJ) memory cell as a sense reference voltage signal;
a second stage sense amplifier configured to compare said sense data voltage signal and said sense reference voltage signal and output a data signal; and
a capturing latch circuit configured to capture said data signal using positive feedback;
wherein said body voltage sensing is performed in response to a body-connected load that provides a high sensing margin (SM) in which body and drain terminals of a transistor of said body voltage sensing data circuit are coupled together.