IP Library Granted Patent US 8,922,013
Granted Patent B2
US 8,922,013 · App. 13/291,788 · Granted Dec 30, 2014

Through via package

Inventors: How Yuan Hwang (Sitiawan, MY); Kah Wee Gan (Singapore, SG)
Assignee: STMicroelectronics Pte Ltd.
H01L23/3171H01L23/49827H01L23/3121H01L24/18H01L21/4857H01L23/5389H01L23/3128H01L23/49816H01L2224/12105
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Quick Facts
Patent No.
US 8,922,013
App. No.
13/291,788
Granted
Dec 30, 2014
Kind
B2
Abstract

An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

Claims (32)

1. A method, comprising:

forming a first conductive redistribution line overlying an active side of an integrated circuit die;

forming a through via from the active side of the integrated circuit die to an inactive side of the integrated circuit die, the through via being electrically connected to the first conductive redistribution line;

placing a first solder ball on the first conductive redistribution line;

placing a first encapsulation layer on the first solder ball;

forming, after placing the first encapsulation layer, a second conductive redistribution line overlying the inactive side of the integrated circuit die in electrical contact with the through via;

removing a portion of the encapsulation layer; and

placing a second solder ball on the first solder ball.

2. The method of claim 1 wherein removing a portion of the insulating material comprises grinding the insulating material and the first solder ball.

3. The method of claim 1 wherein forming the second conductive redistribution line comprises:

depositing a metal layer on the inactive side; and

etching the metal layer to form the second conductive redistribution line, prior to removing the portion of the insulating material.

4. The method of claim 1 , comprising placing a third solder ball on the second conductive redistribution line.

5. The method of claim 4 , comprising covering the third solder ball in a second encapsulation layer.

6. The method of claim 5 , comprising removing a portion of the second encapsulation layer and the third solder ball.

7. The method of claim 6 , comprising placing a fourth solder ball on the third solder ball.

8. The method of claim 1 , comprising:

placing the integrated circuit die in a reconstituted substrate; and

forming the through via in the reconstituted substrate.

9. The method of claim 1 wherein:

forming the first redistribution line includes forming a plurality of first redistribution lines overlying the active side of the integrated circuit die;

forming the second redistribution line includes forming a plurality of second redistribution lines overlying the inactive side of the integrated circuit die; and

forming the through via includes forming a plurality of through vias each electrically connecting a respective one of the plurality of first redistribution lines to a respective one of the plurality of second redistribution lines.

10. A method, comprising:

forming first metal contacts overlying an active side of an integrated circuit die;

covering the active side of the integrated circuit die in a first encapsulation layer; and

forming second metal contacts overlying an inactive side of the integrated circuit die while the active side of the die is covered in the first encapsulation layer.

11. The method of claim 10 , comprising placing first solder balls on the first integrated circuit die prior to covering the active side in the first encapsulation layer.

12. The method of claim 11 , comprising:

removing a portion of the first encapsulation layer and the first solder balls; and

placing second solder balls on the first solder balls after the portion of the first solder balls is removed.

13. The method of claim 12 , comprising placing third solder balls on the second metal contacts.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068433/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2011
From: HWANG, HOW YUAN; GAN, KAH WEE
To: STMICROELECTRONICS PTE LTD.
Reel/Frame 027194/0638 →
Continuity (1)
Related Publication 20130113098A1 · May 9, 2013