Wafer level semiconductor package
There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.
1. A wafer level semiconductor package comprising:
a wafer including a post fabrication redistribution layer (post-Fab RDL) formed between first and second dielectric layers, at least one of said first and second dielectric layers being a pre-formed dielectric layer comprising an Ajinomoto™ Build-up Film (ABF).
2. The wafer level semiconductor package of claim 1 , further comprising a window that receives an electrical contact body in said second dielectric layer, said window exposing said post-Fab RDL.
3. The wafer level semiconductor package of claim 1 , further comprising a window that receives an electrical contact body in said second dielectric layer, said window exposing said post-Fab RDL.
4. The wafer level semiconductor package of claim 1 , further comprising:
a window in said second dielectric layer exposing said post-Fab RDL; and
an under-bump metallization (UBM) in said window that receives an electrical contact body.
5. The wafer level semiconductor package of claim 1 , further comprising:
a window in said second dielectric layer exposing said post-Fab RDL; and
a solder ball received in said window so as to be electrically coupled to said post-Fab RDL.
6. The wafer level semiconductor package of claim 1 , wherein said pre-formed dielectric layer is laminated over a surface of said wafer.
7. A wafer level semiconductor package comprising:
first and second dielectric layers affixed over a surface of a wafer, at least one of said first and second dielectric layers being a pre-formed dielectric layer;
a post-fabrication redistribution layer (post-Fab RDL) between said first and second dielectric layers;
an under-bump metallization (UBM); and
a window that receives an electrical contact body in said second dielectric layer, said window exposing said post-Fab RDL.
8. The wafer level semiconductor package of claim 7 , wherein said pre-formed dielectric layer comprises a build-up material.
9. The wafer level semiconductor package of claim 7 , wherein said pre-formed dielectric layer comprises an Ajinomoto™ Build-up Film (ABF).
10. The wafer level semiconductor package of claim 7 , wherein said pre-formed dielectric layer is laminated over said surface of said wafer.
11. The wafer level semiconductor package of claim 7 , wherein said electrical contact body is a solder ball.
12. The wafer level semiconductor package of claim 1 , wherein said first dielectric layer is between said wafer and said second dielectric layer.
13. The wafer level semiconductor package of claim 1 , wherein said wafer further includes a surface passivation layer.
14. The wafer level semiconductor package of claim 1 , wherein
said wafer further includes an in-fabrication redistribution layer (in-Fab RDL), and
said post-Fab RDL is in contact with said in-Fab RDL.
15. The wafer level semiconductor package of claim 1 , wherein both the first and second dielectric layers are pre-formed dielectric layers.
16. The wafer level semiconductor package of claim 4 , wherein said UBM in said window receives a solder ball so that the solder ball is electrically connected to said post-Fab RDL.
17. The wafer level semiconductor package of claim 7 , wherein said first dielectric layer is between said wafer and said second dielectric layer.
18. The wafer level semiconductor package of claim 7 , wherein said wafer includes a surface passivation layer.
19. The wafer level semiconductor package of claim 7 , wherein
said wafer further includes an in-fabrication redistribution layer (in-Fab RDL), and
said post-Fab RDL is in contact with said in-Fab RDL.
20. The wafer level semiconductor package of claim 7 , wherein both the first and second dielectric layers are pre-formed dielectric layers.
21. A wafer level semiconductor package comprising:
a post fabrication redistribution layer (post-Fab RDL) formed between first and second dielectric layers that are affixed over a surface of a wafer, the first dielectric layer being a pre-formed dielectric layer between the wafer and the second dielectric layer; and
a window that receives an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL.
22. A wafer level semiconductor package comprising:
a post fabrication redistribution layer (post-Fab RDL) formed between first and second dielectric layers that are affixed over a surface of a wafer, the first dielectric layer being a pre-formed dielectric layer between the wafer and the second dielectric layer,
wherein the pre-formed dielectric layer comprises a build-up material.