Power factor correction circuit with frequency jittering

1. A power factor correction circuit, comprising:

a) an inductor current detection circuit configured to detect inductor current flowing through an inductor to generate a sampling voltage signal, and to generate a sinusoidal half-wave current signal and a sinusoidal half-wave voltage signal based on said sampling voltage signal;

b) a mediate signal generator configured to generate a slope voltage signal and a clock signal in response to said sinusoidal half-wave voltage signal, wherein a frequency of each of said slope voltage signal and said clock signal varies with said sinusoidal half-wave voltage signal;

c) a current modulation circuit configured to receive said sinusoidal half-wave current signal and a voltage feedback signal representative of an output voltage of a power stage to generate a regulation signal, wherein said regulation signal is configured to be compared against said slope voltage signal to generate a modulation signal; and

d) a logic and driving circuit configured to receive said modulation signal and said clock signal, and to generate a controlling signal therefrom, wherein said controlling signal is configured to control a power switch to operate with variable frequency to maintain said inductor current substantially in phase with said sinusoidal half-wave voltage signal and said output voltage of said power stage constant.

2. The power factor correction circuit of claim 1 , wherein said inductor current detection circuit comprises:

a) a sinusoidal half-wave current signal generator configured to convert said sampling voltage signal to said sinusoidal half-wave current signal; and

b) a sinusoidal half-wave voltage signal generator configured to generate said sinusoidal half-wave voltage signal based on said sampling voltage signal.

3. The power factor correction circuit of claim 2 , wherein said sinusoidal half-wave current signal generator comprises:

a) a first differential amplifier having inverting and non-inverting input terminals, wherein said inverting input terminal is coupled to ground, and wherein said non-inverting input terminal is configured to receive said sampling voltage signal through a first resistor, and to generate a first differential amplifying signal; and

b) a first current mirror circuit having a first transistor, a second transistor, and a third coupled in a cascade mode, wherein said first differential amplifying signal is configured as a gate driving signal for said first, second, and third transistors, wherein a drain of said first transistor is coupled to said non-inverting input terminal and a drain current of said third transistor is configured as said sinusoidal half-wave current signal.

4. The power factor correction circuit of claim 3 , wherein said sinusoidal half-wave voltage signal generator comprises:

a) a second resistor coupled between a drain of said second transistor and ground; and

b) a third resistor coupled between a drain of said second transistor and a first terminal of a first capacitor that outputs said sinusoidal half-wave voltage signal, wherein a second terminal of said first capacitor is coupled to ground.

5. The power factor correction circuit of claim 1 , wherein said mediate signal generator comprises:

a) a second voltage-current converting circuit configured to convert said sinusoidal half-wave voltage signal to a modulation current signal;

b) a slope voltage signal generator configured to generate said slope voltage signal with variable frequency in response to said modulation current signal;

c) a first comparator configured to compare said slope voltage signal against an upper limit reference voltage, and to generate a set signal therefrom;

d) a second comparator configured to compare said slope voltage signal against a lower limit reference voltage, and to generate a reset signal therefrom; and

e) a first trigger configured to receive said set and reset signals, and to generate said clock signal with variable frequency to control a frequency of said slope voltage signal.

6. The power factor correction circuit of claim 5 , wherein said second voltage-current converting circuit comprises:

a) a second differential amplifier having second inverting and non-inverting input terminals, wherein said second inverting input terminal is configured to receive said sinusoidal half-wave voltage signal, and wherein said second non-inverting input terminal is coupled to ground through a fourth resistor to output a second differential amplifying signal; and

b) a second current mirror circuit having a fourth transistor and a fifth transistor that are coupled in cascade mode, wherein said second differential amplifying signal is configured as a gate driving signal for each of said fourth and fifth transistors, wherein sources of each of said fourth and fifth transistors are coupled to a first reference voltage, wherein a drain of said fourth transistor is coupled to ground through said fourth resistor, wherein a common node signal of said drain of said fourth transistor and said third resistor is coupled to said second non-inverting input terminal, and wherein a drain current of said fifth transistor is configured as said modulation current signal.

7. The power factor correction circuit of claim 5 , wherein said slope voltage signal generator comprises:

a) a second capacitor having a first terminal coupled to a first reference current source and said second voltage-current converting circuit, said second capacitor having a second terminal coupled to ground;

b) a first switch configured to be controlled by said clock signal;

c) a second reference current source coupled in series with said first switch between said first terminal of said second capacitor and ground; and

d) wherein said modulation current signal and said first reference current source are configured as a charging current of said second capacitor, and said second reference current source is configured as a discharging current of said second capacitor to generate said slope voltage signal at a common node of said first reference current source and second capacitor.

8. The power factor correction circuit of claim 5 , wherein said slope voltage signal generator comprises:

a) a first reference current source coupled to a first terminal of a second capacitor, wherein a second terminal of said second capacitor is coupled to ground;

b) a first switch configured to be controlled by said clock signal, wherein said first switch and a second reference current source are coupled in series between said first terminal of said second capacitor and ground; and

c) wherein said first reference current source is configured as a charging current of said second capacitor, and said second reference current source is configured as a discharging current of said second capacitor to generate said slope voltage signal at a common node of said first reference current source and said second capacitor.

9. The power factor correction circuit of claim 8 , wherein said upper limit reference voltage is unstable, and wherein said mediate signal generator further comprises:

a) an unstable upper limit reference voltage generator having a third reference current source coupled to a first terminal of a fifth resistor, wherein a second terminal of said fifth resistor is coupled to ground;

b) wherein a common node of said third reference current source and said fifth resistor is configured to receive said modulation current signal and said third reference current source; and

c) wherein a voltage of a common node of said third reference current source and said fifth resistor is configured as an unstable upper limit reference voltage signal coupled to said non-inverting input terminal of said first comparator.

10. The power factor correction circuit of claim 1 , wherein said logic and driving circuit comprises:

a) a second trigger configured to receive said modulation signal and said clock signal, and to generate a controlling signal therefrom; and

b) a buffering circuit configured to control said operation of said power switch in accordance with said controlling signal.

11. An AC/DC power supply, comprising:

a) the power factor correction circuit of claim 1 ;

b) a rectifier circuit configured to generate a sinusoidal input voltage in response to a received AC voltage; and

c) said power stage having said inductor, said power switch, a rectifier switch, and an output filtering circuit, wherein said power stage is configured to receive said sinusoidal input voltage, and to generate said output voltage.