Method and apparatus for analog-to-digital converter
Aspects of the disclosure provide an analog-to-digital converter (ADC). The ADC includes a comparator module and a digital-to-analog converter (DAC). The comparator module is configured to compare a first voltage sampled from an analog signal and a second voltage output from the digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison. The DAC is configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage.
1. An analog-to-digital converter (ADC), comprising:
a comparator module configured to compare a first voltage sampled from an analog signal and a second voltage output from a digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison wherein the comparator module is configured to select one of a pair of output signals based on the result of the comparison and output the pulse in the selected output signal; and
the DAC configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage.
2. The ADC of claim 1 , wherein the comparator module is configured to avoid a pulse output from the non-selected output signal at the same time with the selected output signal.
3. The ADC of claim 1 , wherein the comparator module further comprises:
a reset control circuit configured to reset circuits in the comparator module in response to the pulse.
4. The ADC of claim 3 , wherein the comparator module resets at the same time the DAC settles the second voltage.
5. The ADC of claim 1 , wherein the DAC comprises multiple switching units corresponding to digital bits of a digital value, and the multiple switching units are enabled in a chain to switch based on pulses output from the comparator module.
6. The ADC of claim 5 , wherein the switching unit is configured to enable a next switching unit in the chain to switch based on a next pulse output from the comparator module.
7. The ADC of claim 1 , wherein the comparator module does not output a clock signal.
8. A method, comprising:
comparing a first voltage sampled from an analog signal with a second voltage settled by a digital-to-analog converter (DAC);
selecting an output signal out of a pair of output signals based on the result of the comparison;
generating a pulse in the selected output signal to indicate a result of the comparison; and
enabling a switching unit in the DAC corresponding to a digital bit to switch a state based on the pulse.
9. The method of claim 8 , further comprising:
avoiding a pulse output from the non-selected signal at the same time with the selected output signal.
10. The method of claim 8 , further comprising:
resetting circuits for a next comparison in response to the pulse.
11. The method of claim 10 , further comprising:
settling the second voltage output from the DAC at the same time of resetting the circuits.
12. The method of claim 8 , wherein enabling the switching unit in the DAC corresponding to the digital bit to switch the state based on the pulse further comprises:
sequentially enabling switching units coupled in a chain corresponding to digital bits of a digital value to switch based on pulses.
13. The method of claim 12 , further comprising:
enabling a next switching unit in the chain to switch based on a next pulse.
14. An integrated circuit (IC) chip having an analog-to-digital converter (ADC), the ADC comprising:
a comparator module configured to compare a first voltage sampled from an analog signal and a second voltage output from a digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison, wherein the comparator module is configured to select an output signal out of a pair of output signals based on the result of the comparison and output the pulse in the selected output signal: and
the DAC configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage.
15. The IC chip of claim 14 , wherein the comparator module is configured to avoid a pulse output from the non-selected output signal at the same time with the selected output signal.
16. The IC chip of claim 14 , wherein the comparator module further comprises:
a reset control circuit configured to reset circuits in the comparator module in response to the pulse at the same time the DAC settles the second voltage.
17. IC chip of claim 14 , wherein the DAC comprises multiple switching units corresponding to digital bits of a digital value, and the multiple switching units are enabled in a chain to switch based on pulses output from the comparator module.