Method and apparatus for scrambling sequence generation in a communication system

1. A wireless communications method, comprising:

employing a processor executing computer executable instructions stored on a computer readable storage medium to implement the following acts:

generating cyclic shifts for a sequence generator by masking output values from a shift register with one or more masking vectors;

generating one or more m-parameters for the sequence generator in accordance with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

forwarding the sequence generator to a desired future sequence state based in part on the output values, the generated one or more m-parameters, and the one or more masking vectors, wherein forwarding the sequence generator to a desired future sequence state comprises:

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employing the generated sequence of bits to initialize the shift register.

2. The method of claim 1 , the vectors are associated with a multi-bit polynomial.

3. The method of claim 1 , wherein the one or more m-parameters are combined as a set to form a Gold sequence.

4. The method of claim 3 , the Gold sequence is formed by an exclusive OR operation of at least two sets of the one or more m-parameters.

5. The method of claim 1 , further comprising generating the cyclic shifts via a modulo-2 adder.

6. The method of claim 5 , generating an additional polynomial value via the modulo-2 adder.

7. The method of claim 1 , further comprising generating one or more sequence hopping functions.

8. The method of claim 1 , further comprising generating one or more cell-specific sequence hopping functions.

9. The method of claim 1 , further comprising generating one or more resource specific sequence hopping functions.

10. The method of claim 1 , further comprising generating one or more orthogonal cover hopping functions.

11. The method of claim 1 , further comprising applying an index hopping sequence if sequence hopping is enabled.

12. A communications apparatus, comprising:

a memory that retains instructions for generating cyclic shifts for a sequence generator by combining output values from a shift register with one or more masking vectors, generating one or more m-parameters for the sequence generator in accordance with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters, and starting the sequence generator at a desired future state based in part on the output values, the generated one or more m-parameters and the one or more masking vectors, wherein the instructions for starting the sequence generator at a desired future state comprise instructions for generating a sequence of bits occurring just before the desired future state, using the one or more parameters, and employing the generated sequence of bits to initialize the shift register; and

a processor that executes the instructions.

13. The apparatus of claim 12 , wherein the one or more m-parameters are combined as a set to form a Gold sequence.

14. The apparatus of claim 13 , the Gold sequence is formed by an exclusive OR operation of at least two sets of the one or more m-parameters.

15. The apparatus of claim 12 , further comprising a modulo-2 adder to generate the cyclic shifts.

16. A communications apparatus, comprising:

means for shifting output values from a register with one or more masking vectors;

means for generating one or more m-parameters in accordance with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

means for setting a desired future sequence state based in part on the output values, the generated one or more m-parameters, and the one or more masking vectors, wherein the means for setting a desired future sequence state is configured to:

generate a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employ the generated sequence of bits to initialize the shift register.

17. The apparatus of claim 16 , wherein the one or more m-parameters are associated with a set of sequences that are employed to form a Gold sequence.

18. A non-transitory computer-readable medium, comprising instructions for:

masking output values from a shift register with one or more masking vectors;

generating one or more m-parameters in accordance with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

setting a sequence generator to a desired future sequence state based in part on the output values, the generated one or more m-parameters, and the one or more masking vectors, wherein the instructions for setting a sequence generator to a desired future sequence state comprises instructions for:

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employing the generated sequence of bits to initialize the shift register.

19. The computer-readable medium of claim 18 , employing an adder to perform a cyclic shift operation.

20. The computer-readable medium of claim 18 , further comprising configuring the sequence generator via a polynomial value.

21. A processor that executes the following instructions for:

adjusting output values from a shift register according to one or more masking vectors;

sequencing one or more m-parameters with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

clocking a sequence generator to a desired future sequence state based in part on the output values, the sequenced one or more m-parameters, and the one or more masking vectors, wherein the instructions for clocking a sequence generator to a desired future sequence state comprises instructions for:

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employing the generated sequence of bits to initialize the shift register.

22. The processor of claim 21 , further comprising generating a Gold sequence from at least two m-sequences.

23. A wireless communication method, comprising:

employing a processor executing computer executable instructions stored on a computer readable storage medium to implement the following acts:

generating a first masking vector from a sequence generator polynomial and a first cyclic shift;

generating a second masking vector from the sequence generator polynomial and a second cyclic shift;

generating one or more m-parameters in accordance with the first and second masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

employing the first and second masking vector to mask output values from a shift register to obtain a first output value and a second output value,

the first output value, the second output value, the masking vectors and the generated one or more m-parameters employed to generate a desired future sequence state, wherein generating the desired future sequence state comprises:

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employing the generated sequence of bits to initialize the shift register.

24. The method of claim 23 , further comprising adding results of the first output value to create a first random sequence.

25. The method of claim 23 , further comprising adding results of the second output value to create a second random sequence.

26. An apparatus operable in wireless communication system, comprising:

means for generating a first masking vector from a sequence generator polynomial and a first cyclic shift;

means for generating a second masking vector from the sequence generator polynomial and a second cyclic shift;

means for generating one or more m-parameters in accordance with the first and second masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

means for processing the first and second masking vector to mask output values from a shift register to obtain a first output value and a second output value that are employed with the masking vectors and the generated one or more m-parameters to generate a desired future sequence state, wherein the means for processing is configured to:

generate a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters; and

employ the generated sequence of bits to initialize the shift register.

27. The apparatus of claim 26 , further comprising a component to add results of the first output value to create a first random sequence and for adding results of the second output value to create a second random sequence.

28. A non-transitory computer-readable medium comprising instructions which, when executed by a computer, cause the computer to perform operations including:

generating a first masking vector from a sequence generator polynomial and a first cyclic shift;

generating a second masking vector from the sequence generator polynomial and a second cyclic shift;

employing the first and second masking vector to mask output values from a shift register to obtain a first output value and a second output value;

generating one or more m-parameters in accordance with the first and second masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

generating a desired future sequence state based on the first and second output values, the first and second masking vectors and the generated one or more m-parameters, wherein generating a future sequence state comprises;

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters, and

employing the generated sequence of bits to initialize the shift register.

29. The computer-readable medium of claim 28 , further comprising generating a Gold sequence from at least two m-sequences.

30. An apparatus operable in a wireless communication system, comprising:

a processor, configured for:

generating a first masking vector from a sequence generator polynomial and a first cyclic shift;

generating a second masking vector from the sequence generator polynomial and a second cyclic shift;

generating one or more m-parameters in accordance with the first and second masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters;

employing the first and second masking vectors to mask output values from a shift register to obtain a first output value and a second output value; and

generating a desired future sequence state from the generated one or more m-parameters, the first and second masking vectors and the shift register output values, wherein the processor is configured to generate the desired future sequence state by:

generating a sequence of bits occurring just before the desired future sequence state, using the one or more m-parameters, and

employing the generated sequence of bits to initialize the shift register.

31. The apparatus of claim 30 , further comprising generating at least one Gold sequence value.

32. A communications method, comprising:

employing a processor executing computer executable instructions stored on a computer readable storage medium to implement the following acts:

generating cyclic shifts for a sequence generator by masking output values from a shift register with one or more masking vectors;

generating one or more m-parameters in accordance with the one or more masking vectors, wherein different mask values are applied to at least two sets of the one or more m-parameters; and

forwarding pseudorandom sequences within the sequence generator by setting a shift register state to a desired future state based on the output values, the generated one or more m-parameters and the one or more vectors, wherein setting the shift register to the desired future state comprises:

generating a sequence of bits occurring just before the desired future state, using the one or more m-parameters, and

employing the generated sequence of bits to initialize the shift register.

33. The method of claim 32 , the future state depends on a generating polynomial, a number of steps of forwarding required, or an initial state.

34. The method of claim 32 , further comprising using the one or more m-parameters to generate a consecutive sequence of bits occurring before the desired future state, employing the bits to initialize the shift register state.