Tap adaptation with a fully unrolled decision feedback equalizer
Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
1. A method comprising:
setting a reference voltage for each one of a plurality of data recovery comparators to a corresponding initial value;
setting a reference voltage for an adaptation comparator to an initial value;
generating, by the adaptation comparator, a detected bit value for each sample of a received signal in a window of n received samples, n being a positive integer;
tracking (i) a number of detected bits having a logic 0 value, and (ii) a number of detected bits having a logic 1 value;
adjusting, based on a ratio of the number of detected bits having a logic 0 value to the number of detected bits having a logic 1 value, the reference voltage for the adaptation comparator by a step size;
selecting one of the data recovery comparators based on a bit history of the n samples; and
setting the reference voltage for the selected one of the data recovery comparators to substantially equal the reference voltage for the adaptation comparator.
2. The method of claim 1 , wherein the step of adjusting the reference voltage for the adaptation comparator comprises:
if the number of detected bits having a logic 0 value is greater than the number of detected bits having a logic 1 value:
decreasing the reference voltage of the adaptation comparator by a step size.
3. The method of claim 1 , wherein the step of adjusting the reference voltage for the adaptation comparator comprises:
if the number of detected bits having a logic 1 value is greater than the number of detected bits having a logic 0 value:
increasing the reference voltage of the adaptation comparator by a predetermined step size.
4. The method of claim 1 , wherein the step of adjusting the reference voltage for the adaptation comparator comprises:
if the number of detected bits having a logic 0 value is substantially equal to the number of detected bits having a logic 1 value:
suspending the adjusting of the reference value of the adaptation comparator.
5. The method of claim 1 , wherein the step size comprises one or more predetermined step sizes for adjustment of the reference voltage of the adaptation comparator.
6. The method of claim 5 , comprising storing values of the one or more predetermined step sizes in one or more stepsize registers.
7. The method of claim 1 , wherein setting the reference voltage for each of the data recovery comparators to a corresponding initial value comprises:
setting the reference voltage for each of the data recovery comparators to a voltage substantially equal to 0.
8. The method of claim 1 , wherein the step of setting a reference voltage for each of the data recovery comparators to a corresponding initial value comprises:
setting the reference voltage for each of the data recovery comparators to an estimated initial voltage, thereby reducing tap adaptation time.
9. The method of claim 1 , wherein each of the one or more data recovery comparators corresponds to a given bit history of the received signal decided by a decision feedback equalizer responsive to the data recovery comparators.
10. The method of claim 9 , wherein the step of setting a reference voltage for each of the data recovery comparators to a corresponding initial value comprises:
setting the reference voltage for each of the data recovery comparators to a midpoint value between first and second voltage levels corresponding to the bit history of the corresponding data recovery comparator.
11. The method of claim 10 , further comprising the step of:
weighting the reference voltage for each of the data recovery comparators by a corresponding inter-symbol interference value;
wherein the inter-symbol interference value is determined by summing pulse responses for a number of previous bits decided by the decision feedback equalizer, the number of previous bits corresponding to the number of taps of the decision feedback equalizer.
12. The method of claim 11 , wherein the decision feedback equalizer has t taps, where t is a positive integer, and the reference voltage, Vref, is given by:
if the cursor bit is equal to 1, Vref=(h −t +h −t−1 + . . . h −1 )+h 0 , where the (h −t h t−1 , . . . h −1 ) represent the pulse response, and h 0 represents the pulse response of the cursor; and
if the cursor bit is equal to 0, Vref=(h −t +h −t−1 + . . . h −1 )−h 0 .
13. A communication system comprising:
a transmitting device configured to transmit a signal over a communication channel to a receiver of the communication system;
a plurality of data recovery comparators of the receiver responsive to samples of an input signal, each data recovery comparator having a corresponding reference voltage;
a decision feedback equalizer of the receiver responsive to the data recovery comparators;
an adaptation comparator of the receiver responsive to the input signal samples and a reference voltage, the adaptation comparator configured to generate a detected bit value for each input signal sample in a window of n received input signal samples, n being a positive integer; and
an adaptation module of the receiver configured to:
track (i) a number of detected bits having a logic 0 value, and (ii) a number of detected bits having a logic 1 value;
adjust, based on a ratio of the number of detected bits having a logic 0 value to the number of detected bits having a logic 1 value, the reference voltage for the adaptation comparator by a step size;
select one of the data recovery comparators based on a bit history of the n samples; and
set the reference voltage for the selected one of the data recovery comparators to substantially equal the reference voltage for the adaptation comparator.
14. The communication system of claim 13 , the tap adaptation module further configured to:
if the number of detected bits having a logic 0 value is greater than the number of detected bits having a logic 1 value:
decrease the reference voltage of the adaptation comparator by a step size;
if the number of detected bits having a logic 1 value is greater than the number of detected bits having a logic 0 value:
increase the reference voltage of the adaptation comparator by a step size; and
if the detected number of bits having a logic 0 value is substantially equal to the detected number of bits having a logic 1 value:
suspend the adjusting of the reference value of the adaptation comparator.
15. The communication system of claim 14 , wherein the decision feedback equalizer has t taps, t a positive integer, the tap adaptation module comprising 2 t +1 stepsize registers, each stepsize register configured to store a predetermined step size for 2 t data recovery comparators.
16. The communication system of claim 13 , the tap adaptation module further configured to:
set the reference voltage for each of one or more data recovery comparators to a voltage substantially equal to 0.
17. The communication system of claim 13 , the tap adaptation module further configured to:
set the reference voltage for each of one or more data recovery comparators to an estimated initial voltage, thereby reducing tap adaptation time.
18. The communication system of claim 13 , wherein each of the one or more data recovery comparators corresponds to a possible bit history of the received signal decided by the decision feedback equalizer.
19. The communication system of claim 18 , the tap adaptation module further configured to:
set the reference voltage for each of one or more data recovery comparators to a midpoint value between first and second voltage levels corresponding to the bit history of the corresponding data recovery comparator.
20. The communication system of claim 19 , the tap adaptation module further configured to:
determine an inter-symbol interference value given by summing pulse responses for a number of previous bits decided by the decision feedback equalizer, the number of previous bits corresponding to the number of taps of the decision feedback equalizer; and
weight the reference voltage for each of the data recovery comparators by the corresponding inter-symbol interference value.
21. The communication system of claim 20 , wherein the decision feedback equalizer has t taps, where t is a positive integer, and the reference voltage, Vref, is given by:
if the cursor bit is equal to 1, Vref=(h −t +h −t−1 + . . . h −1 )+h 0 , where the (h −t , h −t−1 , . . . h −1 ) represent the pulse response, and h 0 represents the pulse response of the cursor; and
if the cursor bit is equal to 0, Vref=(h −t +h −t−1 + . . . h −1 )−h 0 .
22. A receiver comprising:
a plurality of data recovery comparators responsive to samples of an input signal, each data recovery comparator having a corresponding reference voltage;
a decision feedback equalizer responsive to the data recovery comparators;
an adaptation comparator responsive to the input signal samples and a reference voltage, the adaptation comparator configured to generate a detected bit value for each input signal sample in a window of n received input signal samples, n being a positive integer; and
an adaptation module configured to:
track (i) a number of detected bits having a logic 0 value, and (ii) a number of detected bits having a logic 1 value;
adjust, based on a ratio of the number of detected bits having a logic 0 value to the number of detected bits having a logic 1 value, the reference voltage for the adaptation comparator by a step size;
select one of the data recovery comparators based on a bit history of the n samples; and
set the reference voltage for the selected one of the data recovery comparators to substantially equal the reference voltage for the adaptation comparator.
23. The receiver of claim 22 , the tap adaptation module further configured to:
if the number of detected bits having a logic 0 value is greater than the number of detected bits having a logic 1 value:
decrease the reference voltage of the adaptation comparator by a predetermined step size;
if the number of detected bits having a logic 1 value is greater than the number of detected bits having a logic 0 value:
increase the reference voltage of the adaptation comparator by a predetermined step size; and
if the number of detected bits having a logic 0 value is substantially equal to the number of detected bits having a logic 1 value:
suspend the adjusting of the reference value of the adaptation comparator.
24. The receiver of claim 23 , wherein-the decision feedback equalizer has t taps, t a positive integer, the tap adaptation module comprising 2 t +1 stepsize registers, each stepsize register configured to store a predetermined step size for 2 t data recovery comparators.
25. The receiver of claim 22 , wherein each of the one or more data recovery comparators corresponds to a possible bit history of the received signal decided by the decision feedback equalizer.
26. The receiver of claim 25 , the tap adaptation module further configured to:
set the reference voltage for each of one or more data recovery comparators to a midpoint value between first and second voltage levels corresponding to the bit history of the corresponding data recovery comparator.
27. The receiver of claim 26 , the tap adaptation module further configured to:
determine an inter-symbol interference value given by summing pulse responses for a number of previous bits decided by the decision feedback equalizer, the number of previous bits corresponding to the number of taps of the decision feedback equalizer; and
weight the reference voltage for each of the data recovery comparators by the corresponding inter-symbol interference value.
28. The receiver of claim 27 , wherein the decision feedback equalizer has t taps, where t is a positive integer, and the reference voltage, Vref, is given by:
if the cursor bit is equal to 1, Vref=(h −t +h −t−1 + . . . h −1 )+h 0 , where the (h −t +h −t−1 , . . . h −1 ) represent the pulse response, and h 0 represents the pulse response of the cursor; and
if the cursor bit is equal to 0, Vref=(h −t +h −t−1 + . . . h −1 )−h 0 .