Solid-state imaging device and manufacturing method therefor

1. A solid-state imaging device comprising a plurality of pixels, each including:

a photoelectric conversion unit;

a floating diffusion region;

a transferring transistor including a transferring gate electrode configured to transfer signal charge generated at the photoelectric conversion unit to the floating diffusion region;

an amplifying transistor configured to output a signal based on an amount of electric charge of the floating diffusion region; and

a resetting transistor configured to reset a voltage of the floating diffusion region,

the solid-state imaging device further comprising;

a first semiconductor substrate and a second semiconductor substrate,

wherein a first insulating film is provided on a first principal surface of the first semiconductor substrate,

wherein the first semiconductor substrate includes a first pixel region;

wherein a plurality of photoelectric conversion units and a plurality of floating diffusion regions are arranged in the first pixel region;

wherein a first element isolation portion is provided in the first pixel region, configured to electrically isolate at least a part of the plurality of photoelectric conversion units and at least a part of the plurality of floating diffusion regions from each other;

wherein a second insulating film is provided on the second semiconductor substrate;

wherein the second semiconductor substrate includes a second pixel region;

wherein a plurality of the amplifying transistors and a plurality of the resetting transistors are arranged in the second pixel region;

wherein a second element isolation portion is provided in the second pixel region, configured to electrically isolate at least a part of the plurality of the amplifying transistors and at least a part of the plurality of the resetting transistors from each other;

wherein an interface of a region where the first element isolation portion is provided, between the first semiconductor substrate and the first insulating film, is arranged at a first depth with respect to an interface of a region where the photoelectric conversion unit is arranged, between the first semiconductor substrate and the first insulating film;

wherein an interface of a region where the second element isolation portion is provided, between the second semiconductor substrate and the second insulating film, is arranged at a second depth with respect to an interface of a region where the amplifying transistor is arranged, between the second semiconductor substrate and the second insulating film; and

wherein the first depth is shallower than the second depth.

2. The solid-state imaging device according to claim 1 , wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first semiconductor substrate.

3. The solid-state imaging device according to claim 2 , further comprising:

an electrically-conductive pattern configured to electrically connect the floating diffusion region and a gate electrode of the amplifying transistor,

wherein the first principal surface of the first semiconductor substrate faces a principal surface of the second semiconductor substrate on which the gate electrode of the amplifying transistor is arranged, the electrically-conductive pattern being interposed therebetween.

4. The solid-state imaging device according to claim 1 , wherein the second element isolation portion is one of LOCOS isolation and STI isolation.

5. The solid-state imaging device according to claim 1 , wherein the first element isolation portion is one of PN isolation, mesa-type insulator isolation, and EDI isolation.

6. The solid-state imaging device according to claim 1 , wherein at least two of the plurality of pixels share the floating diffusion region.

7. The solid-state imaging device according to claim 1 , wherein the photoelectric conversion unit comprises:

a second conductivity type first semiconductor region configured to be in contact with the first insulating film;

a first conductivity type second semiconductor region provided on an opposite side of the first semiconductor region, to a side thereof on which the first insulating film is provided; and

a second conductivity type third semiconductor region provided on an opposite side of the second semiconductor region, to a side thereof on which the first semiconductor region is provided.

8. The solid-state imaging device according to claim 7 , wherein the first semiconductor region extends through at least two of the plurality of pixels, and

wherein the first semiconductor region and the floating diffusion region are provided with a predetermined distance therebetween.

9. The solid-state imaging device according to claim 7 , wherein the first semiconductor region extends through at least two of the plurality of pixels, and

wherein the first semiconductor region defines a channel width of the transferring transistor.

10. The solid-state imaging device according to claim 7 , wherein a second conductivity type fourth semiconductor region is provided on a opposite side of the float diffusion region, to the first insulating film, and

wherein when the first semiconductor region and the fourth semiconductor region are projected in a direction of the first insulating film, a region onto which the first semiconductor region is projected doesn't overlap with a region onto which the fourth semiconductor is projected.

11. The solid-state imaging device according to claim 7 , wherein a contact plug configured to supply a voltage to the first semiconductor region or the third semiconductor region is provided in a region other than the first pixel region, but not provided in the first pixel region.

12. The solid-state imaging device according to claim 1 , wherein the floating diffusion regions are provided at a pitch of 3 micrometers or less.

13. A solid-state imaging device comprising a plurality of pixels, each including:

a photoelectric conversion unit;

a floating diffusion region;

a transferring transistor including a transferring gate electrode configured to transfer signal charge generated at the photoelectric conversion unit to the floating diffusion region;

an amplifying transistor configured to output a signal based on an amount of electric charge of the floating diffusion region; and

a resetting transistor configured to reset a voltage of the floating diffusion region,

the solid-state imaging device further comprising;

a first semiconductor substrate and a second semiconductor substrate,

wherein a plurality of photoelectric conversion units and a plurality of floating diffusion regions are arranged in the first semiconductor substrate;

wherein one of PN isolation, mesa-type insulator isolation, or EDI isolation is provided in the first semiconductor substrate, configured to electrically isolate at least a part of the plurality of photoelectric conversion units and at least a part of the plurality of floating diffusion regions from each other;

wherein a plurality of the amplifying transistors and a plurality of the resetting transistors are arranged in the second semiconductor substrate;

wherein one of LOCOS isolation or STI isolation is provided in the second semiconductor substrate, configured to electrically isolate at least a part of the plurality of the amplifying transistors and at least a part of the plurality of the resetting transistors from each other;

wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to a first principal surface of the first semiconductor substrate; and

an electrically-conductive pattern configured to electrically connect the floating diffusion region and a gate electrode of the amplifying transistor,

wherein the first principal surface of the first semiconductor substrate faces a principal surface of the second semiconductor substrate on which the gate electrode of the amplifying transistor is arranged, the electrically-conductive pattern being interposed therebetween.

14. A solid-state imaging device comprising a plurality of pixels, each including:

a photoelectric conversion unit;

a floating diffusion region;

a transferring transistor including a transferring gate electrode configured to transfer signal charge generated at the photoelectric conversion unit to the floating diffusion region;

an amplifying transistor configured to output a signal based on an amount of electric charge of the floating diffusion region; and

a resetting transistor configured to reset a voltage of the floating diffusion region,

the solid-state imaging device further comprising;

a signal processing circuit for processing a signal output from the plurality of pixels; and

a first semiconductor substrate and a second semiconductor substrate,

wherein a first insulating film is provided on a first principal surface of the first semiconductor substrate,

wherein the first semiconductor substrate includes a first pixel region;

wherein a plurality of photoelectric conversion units and a plurality of floating diffusion regions are arranged in the first pixel region;

wherein a first element isolation portion is provided in the first pixel region, configured to electrically isolate at least a part of the plurality of photoelectric conversion units and at least a part of the plurality of floating diffusion regions from each other;

wherein a second insulating film is provided on the second semiconductor substrate;

wherein the second semiconductor substrate includes a second pixel region and a peripheral circuit region;

wherein a plurality of the amplifying transistors and a plurality of the resetting transistors are arranged in the second pixel region;

wherein a plurality of transistors included in the signal processing circuit are arranged in the peripheral circuit region;

wherein a second element isolation portion is arranged in the peripheral circuit region, configured to electrically isolate at least a part of the plurality of transistors from each other;

wherein an interface of a region where the first element isolation portion is provided, between the first semiconductor substrate and the first insulating film, is arranged at a first depth with respect to an interface of a region where the photoelectric conversion unit is arranged, between the first semiconductor substrate and the first insulating film;

wherein an interface of a region where the second element isolation portion is provided, between the second semiconductor substrate and the second insulating film, is arranged at a second depth with respect to an interface of a region where the transistor included in the signal processing circuit is arranged, between the second semiconductor substrate and the second insulating film; and

wherein the first depth is shallower than the second depth.

15. The solid-state imaging device according to claim 14 , wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first semiconductor substrate.

16. The solid-state imaging device according to claim 15 , further comprising:

an electrically-conductive pattern configured to electrically connect the floating diffusion region and a gate electrode of the amplifying transistor,

wherein the first principal surface of the first semiconductor substrate faces a principal surface of the second semiconductor substrate on which the gate electrode of the amplifying transistor is arranged, the electrically-conductive pattern being interposed therebetween.

17. The solid-state imaging device according to claim 14 , wherein the first element isolation portion is one of PN isolation, mesa-type insulator isolation, and EDI isolation, and

wherein the second element isolation portion is one of LOCOS isolation and STI isolation.

18. A solid-state imaging device comprising a plurality of pixels, each including:

a photoelectric conversion unit;

a floating diffusion region;

a transferring transistor including a transferring gate electrode configured to transfer signal charge generated at the photoelectric conversion unit to the floating diffusion region;

an amplifying transistor configured to output a signal based on an amount of electric charge of the floating diffusion region; and

a resetting transistor configured to reset a voltage of the floating diffusion region,

the solid-state imaging device further comprising;

a first semiconductor substrate,

wherein a first insulating film is provided on a first principal surface of the first semiconductor substrate,

wherein the first semiconductor substrate includes a first pixel region;

wherein a plurality of the photoelectric conversion units and a plurality of the floating diffusion regions are arranged in the first pixel region;

wherein a first element isolation portion is arranged in the first pixel region, configured to electrically isolate at least a part of the plurality of photoelectric conversion units and at least a part of the plurality of floating diffusion regions from each other;

wherein a plurality of amplifying transistors and a plurality of resetting regions are arranged in a second pixel region other than the first pixel region;

wherein an interface between the first semiconductor substrate and the first insulating film is substantially flat through the first pixel region; and

wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first semiconductor substrate; and

a second semiconductor substrate; and

an electrically-conductive pattern configured to electrically connect the floating diffusion region and a gate electrode of the amplifying transistor,

wherein the second semiconductor substrate includes the second pixel region, and

wherein the first principal surface of the first semiconductor substrate faces a principal surface of the second semiconductor substrate, on which the gate electrode of the amplifying transistor is arranged, the electrically-conductive pattern being interposed therebetween.