Transistor and method of fabricating the same
A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.
1. A transistor, comprising:
a dielectric layer having a first surface and a second surface;
a gate located on the first surface of the dielectric layer;
an active stacked structure located on the second surface of the dielectric layer, wherein the active stacked structure is consisted of two layers including a first active layer and a second active layer, wherein the second active layer is a top layer of the active stacked structure, a material of the first active layer comprises a first semiconductor and a material of the second active layer comprises a second semiconductor, a composition of the first semiconductor and a composition of the second semiconductor are the same, and a constituent ratio of oxygen of the first semiconductor is lower than a constituent ratio of oxygen of the second semiconductor; and
a source and a drain located on the second surface of the dielectric layer and at two sides of the active stacked structure respectively, wherein the source and the drain extend between the first active layer and the second active layer of the active stacked structure.
2. The transistor of claim 1 , wherein the second active layer of the active stacked structure further comprises an extension portion separating the source from the drain and connecting to the first active layer.
3. The transistor of claim 1 , further comprising a substrate opposite to the first surface of the dielectric layer and covering the gate and the dielectric layer.
4. The transistor of claim 1 , further comprising a substrate opposite to the second surface of the dielectric layer and covering the active stacked structure, the source, the drain and the dielectric layer.
5. The transistor of claim 3 , further comprising a protection layer opposite to the second surface of the dielectric layer and covering the active stacked structure, the source, the drain and the dielectric layer.
6. The transistor of claim 4 , further comprising a protection layer opposite to the first surface of the dielectric layer and covering the gate and the dielectric layer.
7. The transistor of claim 5 , wherein the protection layer is a single layer.
8. The transistor of claim 6 , wherein the protection layer is a single layer.
9. The transistor of claim 5 , wherein the protection layer is a stacked layer.
10. The transistor of claim 6 , wherein the protection layer is a stacked layer.
11. The transistor of claim 5 , wherein the material of the protection layer comprises organic material, inorganic material or hybrid material of the organic material and the inorganic material.
12. The transistor of claim 6 , wherein the material of the protection layer comprises organic material, inorganic material or hybrid material of the organic material and the inorganic material.
13. The transistor of claim 2 , wherein the extension portion of the second active layer further downwardly extend to divide the first active layer into two parts.
14. The transistor of claim 1 , wherein the material of the first semiconductor comprises oxide semiconductor.
15. The transistor of claim 1 , wherein the material of the second semiconductor comprises oxide semiconductor.
16. The transistor of claim 14 , wherein the oxide semiconductor comprises two or more than two constituent elements.
17. The transistor of claim 15 , wherein the oxide semiconductor comprises two or more than two constituent elements.
18. The transistor of claim 1 , wherein one of the source and the drain is electrically connected to a gate of another transistor.
19. A method for manufacturing a transistor, comprising:
forming a gate on a substrate;
forming a dielectric layer on the gate and the substrate;
forming a first active layer of an active stacked structure on the dielectric layer;
forming a source and a drain on the first active layer and the dielectric layer to cover two sides of the first active layer respectively, wherein a space is between the source and the drain and the space exposes the first active layer; and
forming a second active layer of the active stacked structure on the space to cover a portion of the source and a portion of the drain, wherein the second active layer is a top layer of the active stacked structure,
wherein a material of the first active layer comprises a first semiconductor and a material of the second active layer comprises a second semiconductor, a composition of the first semiconductor and a composition of the second semiconductor are the same, and a constituent ratio of oxygen of the first semiconductor is lower than a constituent ratio of oxygen of the second semiconductor.
20. The method of claim 19 , further comprising forming a protection layer to cover the active stacked structure, the source, the drain and the dielectric layer.
21. The method of claim 19 , further comprising removing the first active layer exposed by the space so as to divide the first active layer into two parts after the source and the drain are formed.
22. The method of claim 21 , further comprising performing a surface treatment after the first active layer exposed by the space is removed.
23. The method of claim 22 , wherein the surface treatment comprises a plasma process.
24. The method of claim 23 , wherein the plasma process comprises a hydrogen plasma process, a hydrogen-containing plasma process or an oxygen-containing plasma process.
25. The method of claim 19 , further comprising performing a surface treatment on the first active layer exposed by the space.
26. The method of claim 25 , wherein the surface treatment comprises a plasma process.
27. The method of claim 26 , wherein the plasma process comprises a hydrogen plasma process, a hydrogen-containing plasma process or an oxygen-containing plasma process.
28. A method for manufacturing a transistor, comprising:
forming a first active layer of an active stacked structure on the substrate;
forming a source and a drain on the first active layer and the substrate to cover two sides of the first active layer respectively, wherein a space is between the source and the drain and the space exposes the first active layer;
forming a second active layer of the active stacked structure in the space and to cover a portion of the source and a portion of the drain, wherein the second active layer is a top layer of the active stacked structure;
forming a dielectric layer on the source, the drain, the second active layer and the substrate; and
forming a gate on the dielectric layer,
wherein a material of the first active layer comprises a first semiconductor and a material of the second active layer comprises a second semiconductor, a composition of the first semiconductor and a composition of the second semiconductor are the same, and a constituent ratio of oxygen of the first semiconductor is lower than a constituent ratio of oxygen of the second semiconductor.
29. The method of claim 28 , further comprising forming a protection layer to cover the gate and the dielectric layer.
30. The method of claim 28 , further comprising removing the first active layer exposed by the space so as to divide the first active layer into two parts after the source and the drain are formed.
31. The method of claim 30 , further comprising performing a surface treatment after the first active layer exposed by the space is removed.
32. The method of claim 31 , wherein the surface treatment comprises a plasma process.
33. The method of claim 32 , wherein the plasma process comprises a hydrogen plasma process, a hydrogen-containing plasma process or an oxygen-containing plasma process.
34. The method of claim 28 , further comprising performing a surface treatment on the first active layer exposed by the space.
35. The method of claim 34 , wherein the surface treatment comprises a plasma process.
36. The method of claim 35 , wherein the plasma process comprises a hydrogen plasma process, a hydrogen-containing plasma process or an oxygen-containing plasma process.
37. The transistor of claim 1 , wherein a portion of the source and a portion of the drain are exposed by the second active layer.
38. A transistor, comprising:
a dielectric layer having a first surface and a second surface;
a gate located on the first surface of the dielectric layer;
an active stacked structure located on the second surface of the dielectric layer, wherein the active stacked structure comprises a first active layer and a second active layer, wherein a material of the first active layer comprises a first semiconductor and a material of the second active layer comprises a second semiconductor, a composition of the first semiconductor and a composition of the second semiconductor are the same, and a constituent ratio of oxygen of the first semiconductor is lower than a constituent ratio of oxygen of the second semiconductor; and
a source and a drain located on the second surface of the dielectric layer and at two sides of the active stacked structure respectively, wherein the source and the drain extend between the first active layer and the second active layer of the active stacked structure, the second active layer is a top layer of the active stacked structure, and a portion of a bottom portion of the second active layer is in contact with the source and the drain.