Thin film transistor substrate having metal oxide semiconductor and method for manufacturing the same
The present disclosure relates to a thin film transistor substrate with a metal oxide semiconductor layer that has enhanced characteristics and stability. The present disclosure also relates to a method for manufacturing a thin film transistor substrate in which a thermal treatment is conducted for the metal oxide semiconductor layer and the damages to the substrate by the thermal treatment are minimized.
1. A method of manufacturing a thin film transistor substrate, comprising:
depositing, in sequence, a gate electrode metal material, a gate insulating material, and a metal oxide semiconductor material on a substrate;
conducting a thermal treatment after depositing the gate electrode metal material, the gate insulating material and the metal oxide semiconductor material;
forming a gate electrode, a gate insulating layer, and a semiconductor active layer by patterning the gate electrode metal material, the gate insulating material, and the metal oxide semiconductor material, simultaneously in a single mask process after conducting the thermal treatment;
forming a gate line after forming the gate electrode, the gate line contacting portions of the gate electrode and extending in a horizontal direction on the substrate;
forming an intermediate insulating layer covering the gate line and the gate electrode and exposing middle portions of the semiconductor active layer; and
forming a data line extending in a vertical direction on the intermediate insulating layer, a source electrode branching from the data line and contacting one side of the semiconductor active layer, and a drain electrode facing the source electrode apart from a predetermined distance and contacting other side of the semiconductor active layer.
2. The method according to claim 1 , further comprising:
forming a passivation layer covering the data line, the source electrode, and the semiconductor active layer, and including a pixel contact hole exposing some portions of the drain electrode; and
forming a pixel electrode contacting the drain electrode through the pixel contact hole, on the passivation layer.
3. The method according to claim 2 , further comprising:
before forming the pixel electrode, forming a color filter, on the passivation layer, the color filter filling a pixel area surrounded by the gate line and the data line, and covering areas corresponding to the thin film transistor including the semiconductor active layer; and
forming an overcoat layer covering the color filter.
4. The method according to the claim 1 , wherein the gate line includes a copper material.
5. The method according to the claim 1 , wherein the data line, the source electrode and the drain electrode are formed by depositing a protective layer having molybdenum and a low resistance layer having copper sequentially and patterning the protective layer and the low resistance layer.
6. The method according to the claim 5 , wherein the protective layer including the molybdenum is patterned by a dry-etching process.
7. The method according to the claim 1 , wherein the gate insulating material comprises silicon oxide.
8. The method according to claim 1 , wherein the metal oxide semiconductor material comprises at least one of Indium Gallium Zinc Oxide or Indium Tin Zinc Oxide.
9. The method according to claim 1 , wherein the single process mask uses a half-tone mask.
10. The method according to claim 1 , wherein the thermal treatment is conducted at 300° C. or a higher temperature.