Semiconductor memory device capable of screening a weak bit and repairing the same
A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
1. A semiconductor device comprising:
a first memory region including a plurality of memory cells;
a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and
a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit,
wherein the first memory region and the second memory region include different types of memory cells.
2. The semiconductor device of claim 1 , further comprising a third memory region configured to store the WBA of the first memory region in a non-volatile manner.
3. The semiconductor device of claim 2 , wherein the third memory region includes one of an anti-fuse array and a fuse array.
4. The semiconductor device of claim 1 , wherein the plurality of memory cells of the first memory region include dynamic random access memory (DRAM) cells.
5. The semiconductor device of claim 4 , wherein the weak hit corresponds to a memory cell from among the DRAM cells which has a weak refresh characteristic, a weak cell write characteristic, or a weak data retention characteristic.
6. The semiconductor device of claim 1 , wherein, the test unit is configured to screen the WBA of the first memory region and then, stores the WBA and corresponding data in an error log register.