Generation of constrained pseudo-random binary sequences (PRBS)

1. A method of generating a signal, comprising:

generating an unconstrained random bit sequence;

using a processor to modify the unconstrained random bit sequence to satisfy a constraint, including by:

receiving constraint settings, including: (1) a block length and (2) a maximum number of consecutive events that are permitted to be in a row, wherein an event includes a transition or a run; and

checking that a block, having the specified block length, from the unconstrained random bit sequence does not exceed the specified maximum number of consecutive events, wherein enforcement of the maximum number of consecutive events does not straddle block boundaries; and

outputting the modified random bit sequence.

2. The method of claim 1 , wherein the method is performed by one or more of the following: a tester, a semiconductor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or an embedded microprocessor.

3. The method of claim 1 , wherein the constraint includes one or more of the following: a run length limited (RLL) constraint or a maximum transition run (MTR) constraint.

4. The method of claim 1 , wherein obtaining the unconstrained random bit sequence includes one or more of the following: generating the unconstrained random bit sequence using a seed, generating the unconstrained random bit sequence using a generator polynomial, or generating the unconstrained random bit sequence using a feedback signal associated with modification of the unconstrained random bit sequence to satisfy the constraint.

5. The method of claim 1 , wherein the modified random bit sequence is used to train a detector.

6. The method of claim 5 , wherein the detector includes a soft output Viterbi detector.

7. A system for generating a signal, comprising:

a bit sequence generator configured to generate an unconstrained random bit sequence;

a constraint enforcer configured to modify the unconstrained random bit sequence to satisfy a constraint, including by:

receiving constraint settings, including: (1) a block length and (2) a maximum number of consecutive events that are permitted to be in a row, wherein an event includes a transition or a run; and

checking that a block, having the specified block length, from the unconstrained random bit sequence does not exceed the specified maximum number of consecutive events, wherein enforcement of the maximum number of consecutive events does not straddle block boundaries; and

an interface configured to output the modified random bit sequence.

8. The system of claim 7 , wherein the system includes one or more of the following: a tester, a semiconductor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or an embedded microprocessor.

9. The system of claim 7 , wherein the constraint includes one or more of the following: a run length limited (RLL) constraint or a maximum transition run (MTR) constraint.

10. The system of claim 7 , wherein the processor is configured to obtain the unconstrained random bit sequence, including by one or more of the following: generating the unconstrained random bit sequence using a seed, generating the unconstrained random bit sequence using a generator polynomial, or generating the unconstrained random bit sequence using a feedback signal associated with modification of the unconstrained random bit sequence to satisfy the constraint.

11. The system of claim 7 , wherein the modified random bit sequence is used to train a detector.

12. The system of claim 11 , wherein the detector includes a soft output Viterbi detector.

13. A computer program product for generating a signal, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

generating an unconstrained random bit sequence;

modifying the unconstrained random bit sequence to satisfy a constraint, including by:

receiving constraint settings, including: (1) a block length and (2) a maximum number of consecutive events that are permitted to be in a row, wherein an event includes a transition or a run; and

checking that a block, having the specified block length, from the unconstrained random bit sequence does not exceed the specified maximum number of consecutive events, wherein enforcement of the maximum number of consecutive events does not straddle block boundaries; and

outputting the modified random bit sequence.

14. The computer program product of claim 13 , wherein the computer program product is included in a tester.

15. The computer program product of claim 13 , wherein the constraint includes one or more of the following: a run length limited (RLL) constraint or a maximum transition run (MTR) constraint.

16. The computer program product of claim 13 , wherein the computer instructions for obtaining the unconstrained random bit sequence include computer instructions for one or more of the following: generating the unconstrained random bit sequence using a seed, generating the unconstrained random bit sequence using a generator polynomial, or generating the unconstrained random bit sequence using a feedback signal associated with modification of the unconstrained random bit sequence to satisfy the constraint.

17. The computer program product of claim 13 , wherein the modified random bit sequence is used to train a detector.

18. The computer program product of claim 17 , wherein the detector includes a soft output Viterbi detector.