IP Library Granted Patent US 8,936,985
Granted Patent B2
US 8,936,985 · App. 13/418,128 · Granted Jan 20, 2015

Methods related to power semiconductor devices with thick bottom oxide layers

Inventors: Ashok Challa (Sandy, UT); Alan Elbanhawy (Hollister, CA); Dean E. Probst (West Jordan, UT); Steven P. Sapp (Felton, CA); Peter H. Wilson (Wrightwood, CA); Babak S. Sani (Oakland, CA); Becky Losee (Cedar Hills, UT); Robert Herrick (Lehi, UT); James J. Murphy (South Jordan, UT); Gordon K. Madson (Riverton, UT); Bruce D. Marchant (Murray, UT); Christopher B. Kocon (Murray, PA); Debra S. Woolsey (Draper, UT)
Assignee: Fairchild Semiconductor Corporation
H01L29/407H01L29/66348H01L21/6835H01L29/7813H02M3/33592H01L21/31116H01L2924/01078H01L2924/3011H02M3/00H01L29/7805H01L2924/13055H01L29/1095H01L29/7802H01L2924/01019H01L29/7815H01L2924/3025H02M7/48Y02B70/1475H01L2924/19041H01L29/0661H01L29/4933H01L2224/16H01L29/0623H01L2924/13091H01L29/7831H01L2924/15311H01L29/42368H01L2924/10253H01L2924/1532H01L29/165H01L2221/6834H01L29/402H01L29/0634H01L23/4952H01L29/4236H01L21/30655H01L21/26586H01L29/0653H01L29/4238H01L29/7396H01L2221/68363H01L29/7806H01L2924/01012H01L29/41766H01L2924/30105H01L21/3065H01L29/7811H01L29/495H01L23/49816H01L29/7804H01L29/0696H01L29/7828H01L29/66734
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Quick Facts
Patent No.
US 8,936,985
App. No.
13/418,128
Granted
Jan 20, 2015
Kind
B2
Abstract

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Claims (62)

1. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench;

forming an electrode in the active trench; and

forming a source region, having the first conductivity type, in the well region.

2. The method of claim 1 , wherein the forming the oxide further includes:

forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that substantially fills the active trench and covers at least a portion of a top surface of a semiconductor substrate; and

etching at least a first portion of the oxide film off a top surface of the semiconductor substrate; and

etching at least a second portion of the oxide film from inside the trench leaving a substantially flat layer of the oxide along the bottom of the active trench.

3. The method of claim 1 , wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a temperature treatment to densify at least a portion of the oxide.

4. The method of claim 1 , wherein the forming the oxide further includes:

depositing the oxide by a directional Tetraethoxysilate (TEOS) process that forms a thicker film of the oxide on horizontal surfaces including the bottom of the active trench than vertical surfaces including the first sidewall of the active trench; and

isotropically etching the oxide until all of the oxide on the first sidewall of the active trench is removed leaving the oxide along the bottom of the active trench having a target thickness.

5. The method of claim 1 , wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a dry top oxide etch followed by a wet buffered oxide etch.

6. The method of claim 1 , wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a dry top oxide etch, the dry top oxide etch includes a fog etch process that etches a portion of the oxide near a top edge of the active trench at an accelerated rate as compared to a portion of the oxide near the bottom of the active trench.

7. The method of claim 1 , wherein the forming the oxide along the bottom of the active trench and the oxide along the first sidewall of the active trench includes depositing using a high density plasma deposition process,

the method further comprising:

removing at least a portion of the oxide from the first sidewall of the active trench by a wet etch process such that a profile of the active trench slopes away from the active trench near a top of the active trench.

8. A method, comprising:

forming a trench in a semiconductor substrate;

forming a layer of pad oxide on the semiconductor substrate;

depositing a layer of silicon nitride on the pad oxide;

performing an anisotropic etch to remove silicon nitride from at least a portion of a bottom of the trench and leaving at least a portion of the layer of silicon nitride on a sidewall of the trench;

depositing, using a sub-atmospheric chemical vapor deposition process, an oxide on the portion of the bottom of the trench, the pad oxide, the silicon nitride, and the oxide deposited using the sub-atmospheric chemical vapor deposition process collectively defining at least a portion of a sandwich layer of oxide-nitride-oxide;

removing, using an etch process, the sandwich layer of oxide-nitride-oxide from the sidewall of the trench;

forming a source region adjacent the sidewall of the trench; and

forming a charge control trench laterally spaced from the trench by a mesa region, the charge control trench being aligned parallel to the trench.

9. A method, comprising:

forming a trench in a semiconductor substrate;

forming a layer of pad oxide on the semiconductor substrate including on a sidewall of the trench and on a bottom of the trench;

forming a layer of nitride on top of the pad oxide;

removing a first portion of the layer of nitride from the bottom of the trench and leaving a second portion of the layer of nitride adjacent to the pad oxide on a sidewall of the trench;

removing a portion of the pad oxide exposing a surface of the bottom of the trench;

performing an anisotropic etch of the exposed surface of the bottom of the trench to form a lower trench portion;

forming a layer of oxide in the lower trench portion;

forming at least two electrodes in the trench; and

forming a charge control trench laterally spaced from the trench by a mesa region, the charge control trench being aligned parallel to the trench.

10. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench the forming the oxide includes removing a pad oxide from a plurality of horizontal surfaces including a portion of the bottom of the trench;

forming an electrode in the active trench; and

forming the first source region, having the first conductivity type, in the well region.

11. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench;

forming a first electrode in the active trench;

forming a second electrode disposed in the active trench below the first electrode; and

forming the first source region, having the first conductivity type, in the well region.

12. The method of claim 11 , further comprising:

forming a third electrode in the charge control trench, the active trench including a different number of electrodes than the charge control trench.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2014
From: CHALLA, ASHOK; ELBANHAWY, ALAN; GREBS, THOMAS E.; KRAFT, NATHAN L.; PROBST, DEAN E.; RIDLEY, RODNEY S.; SAPP, STEVEN P.; WANG, QI; YUN, CHONGMAN; LEE, J.G.; WILSON, PETER H.; YEDINAK, JOSEPH A.; JUNG, J.Y.; JANG, H.C.; SANI, BABAK S.; STOKES, RICHARD; DOLNY, GARY M.; MYTYCH, JOHN; LOSEE, BECKY; SELSLEY, ADAM; HERRICK, ROBERT; MURPHY, JAMES J.; MADSON, GORDON K.; MARCHANT, BRUCE D.; REXER, CHRISTOPHER L.; KOCON, CHRISTOPHER B.; WOOLSEY, DEBRA S
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 033833/0697 →
Continuity (5)
Division 12032599 · Feb 15, 2008
Continuation 11026276 · Dec 29, 2004
Continuation In Part 10640742 · Aug 14, 2003
Continuation In Part 10442670 · May 20, 2003
Related Publication 20120220091A1 · Aug 30, 2012