Interface methods and apparatus for memory devices using arbitration
View Patent ↗A disclosed example apparatus includes an interface ( 702, 726 ) to receive a request to access a memory ( 602 a ) of a memory module ( 600 ) and a data store status monitor ( 730 ) to determine a status of the memory. The example apparatus also includes a message output subsystem ( 732 ) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.
1. A memory module, comprising:
an interface to receive a request to access a memory of a memory module;
a data store status monitor to determine a status of the memory;
a message output subsystem to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable; and
a data store access arbiter to, when the memory is busy, determine whether the request can be placed in a queue of the memory, the negative acknowledgment by the message output system being performed when the request cannot be placed in the queue.
2. A memory module as defined in claim 1 , wherein the request cannot be placed in the queue when the queue is filled.
3. A memory module as defined in claim 1 , wherein the request is received and the negative acknowledgement is sent using packet data communications.
4. A memory module as defined in claim 1 , wherein the request to access the memory is a request to write data to the memory.
5. A memory module as defined in claim 4 , wherein the memory is a first memory and the request is received from a second memory to write data to the first memory using a memory-to-memory transfer.
6. A memory module, comprising:
an interface to receive a request to access a memory of a memory module;
a data store status monitor to determine a status of the memory;
a message output subsystem to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable; and
a data store access arbiter to enable immediately servicing the request when the memory is not busy.
7. A memory module as defined in claim 6 , wherein the request is received and the negative acknowledgement is sent using packet data communications.
8. A memory module as defined in claim 6 , wherein the request to access the memory is a request to write data to the memory.
9. A memory module as defined in claim 8 , wherein the memory is a first memory and the request is received from a second memory to write data to the first memory using a memory-to-memory transfer.
10. A method comprising:
receiving a request to access a memory of a memory module;
determining a status of the memory via a status monitor circuit of the memory module;
when the memory is busy, responding to the request with a negative acknowledgement indicating that the request to access the memory is not grantable; and
when the memory is busy, determining via a data store access arbiter circuit whether the request can be placed in a queue of the memory, the negative acknowledgment by the message output system being performed when the request cannot be placed in the queue.
11. A method as defined in claim 10 , wherein the request cannot be placed in the queue when the queue is filled.
12. A method as defined in claim 10 , wherein the request is received and the negative acknowledgement is sent using packet data communications.
13. A method as defined in claim 10 , wherein the request to access the memory is a request to write data to the memory.
14. A method as defined in claim 13 , wherein the memory is a first memory and the request is received from a second memory to write data to the first memory using a memory-to-memory transfer.
15. A method comprising:
receiving a request to access a memory of a memory module;
determining a status of the memory via a status monitor circuit of the memory module;
when the memory is busy, responding to the request with a negative acknowledgement indicating that the request to access the memory is not grantable; and
enabling via a data store access arbiter circuit immediate servicing of the request when the memory is not busy.
16. A method as defined in claim 15 , wherein the request is received and the negative acknowledgement is sent using packet data communications.
17. A method as defined in claim 15 , wherein the request to access the memory is a request to write data to the memory.
18. A method as defined in claim 17 , wherein the memory is a first memory and the request is received from a second memory to write data to the first memory using a memory-to-memory transfer.