IP Library Granted Patent US 8,941,407
Granted Patent B2
US 8,941,407 · App. 13/906,219 · Granted Jan 27, 2015

Integrated circuit with configurable on-die termination

Inventor: Huy Nguyen (San Jose, CA)
Assignee: Rambus Inc.
H04L25/0278H04L25/0298
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Quick Facts
Patent No.
US 8,941,407
App. No.
13/906,219
Granted
Jan 27, 2015
Kind
B2
Abstract

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Claims (32)

1. An integrated-circuit (IC) die comprising:

a first input pad

a second input pad;

a receiver having differential input terminals, including a first input terminal connected to the first input pad and a second input terminal connected to the second input pad; and

programmable on-die termination (ODT) circuitry that includes:

a common node;

a first termination leg extending between the common node and the first input terminal, the first termination leg including a first termination impedance;

a second termination leg extending between the common node and the second input terminal, the second termination leg including a second termination impedance; and

a third termination leg extending between the common node and a reference-voltage node, the third termination leg including a switch.

2. The IC die of claim 1 , wherein at least one of the first termination impedance and the second termination impedance is adjustable.

3. The IC die of claim 1 , wherein the first termination leg includes a second switch connected in series with the first termination impedance and the second termination leg includes a third switch connected in series with the second termination impedance.

4. The IC die of claim 1 , further comprising a memory coupled to the switch to deliver a select signal to the switch.

5. The IC die of claim 4 , wherein the switch includes a transistor having a control terminal, and wherein the memory includes an output connected to the control terminal to deliver the select signal.

6. The IC die of claim 1 , wherein the third termination leg includes a capacitor.

7. The IC die of claim 6 , wherein the capacitor includes a control terminal to control a programmable capacitance, the IC die further including a memory having an output connected to the control terminal.

8. The IC die of claim 6 , wherein the capacitor is connected in series with the switch.

9. The IC die of claim 1 , the third leg further comprising an adjustable termination.

10. The IC die of claim 9 , wherein the adjustable termination comprises a third termination impedance.

11. The IC die of claim 10 , wherein the third termination impedance is connected in series with the switch.

12. The IC die of claim 1 , wherein the reference-voltage node is connected to ground.

13. A computer-readable medium having stored thereon a non-transitory data structure defining an integrated circuit, the data structure comprising:

first data representing first and second input pads to couple to an external signal channel;

second data representing a receiver having differential input terminals, including a first input terminal connected to the first input pad and a second input terminal connected to the second input pad; and

fourth data representing programmable on-die termination (ODT) circuitry that includes:

a common node;

a first termination leg extending between the common node and the first input terminal, the first termination leg including a first termination impedance;

a second termination leg extending between the common node and the second input terminal, the second termination leg including a second termination impedance; and

a third termination leg extending between the common node and a reference-voltage node, the third termination leg including a switch.

14. The medium of claim 13 , wherein the fourth data represents the first termination impedance as a first adjustable impedance and the second termination impedance as a second adjustable impedance.

15. The medium of claim 14 , further comprising fifth data representing a memory coupled to the first termination impedance, the second termination impedance and the switch, the memory to control the switch, the first adjustable impedance, and the second adjustable impedance.

16. The medium of claim 13 , wherein the fourth data represents the third leg as including an adjustable termination.

17. The medium of claim 16 , wherein the adjustable termination comprises a third termination impedance.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2015
From: NGUYEN, HUY
To: RAMBUS INC.
Reel/Frame 034835/0070 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2013
From: NGUYEN, HUY
To: RAMBUS INC.
Reel/Frame 031531/0666 →
Continuity (6)
Continuation 13312762 · Dec 6, 2011
Continuation 13023993 · Feb 9, 2011
Continuation 12790381 · May 28, 2010
Continuation 12288612 · Oct 21, 2008
Continuation 11313054 · Dec 19, 2005
Related Publication 20140139261A1 · May 22, 2014