Peel decoding for concatenated codes
A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.
1. A method for storing data, comprising:
using a processor to encode a set of input data using a first error correction code to obtain a set of first codewords;
interleaving the set of first codewords;
using the processor to encode the interleaved set of first codewords using a second, systematic error correction code associated with a parity matrix having at least some columns which are linearly independent to obtain a set of second codewords, wherein the set of second codewords includes a set of second data portions and a set of second parity portions;
interleaving the set of second parity portions;
using the processor to encode the interleaved set of second parity portions using a third, systematic error correction code to obtain a set of third codewords, wherein the set of third codewords includes a set of third data portions and a set of third parity portions; and
storing, in storage, the set of first codewords and the set of third parity portions, wherein the set of second parity portions which overlaps with the set of third data portions is not stored in storage.
2. The method recited in claim 1 , wherein the method is performed at least in part by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
3. The method recited in claim 1 , wherein the parity matrix has a width of w and the values of the columns includes all values in the range of 1 and w, inclusive.
4. The method recited in claim 1 , wherein the parity matrix includes at least one full copy of a building block parity matrix, at least one partial copy of the building block parity matrix, and at least one copy of an identity matrix.
5. A system for storing data, comprising:
a processor; and
a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:
encode a set of input data using a first error correction code to obtain a set of first codewords;
interleave the set of first codewords;
encode the interleaved set of first codewords using a second, systematic error correction code associated with a parity matrix having at least some columns which are linearly independent to obtain a set of second codewords, wherein the set of second codewords includes a set of second data portions and a set of second parity portions;
interleave the set of second parity portions;
encode the interleaved set of second parity portions using a third, systematic error correction code to obtain a set of third codewords, wherein the set of third codewords includes a set of third data portions and a set of third parity portions; and
store, in storage, the set of first codewords and the set of third parity portions, wherein the set of second parity portions which overlaps with the set of third data portions is not stored in storage.
6. The system recited in claim 5 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
7. The system recited in claim 5 , wherein the parity matrix has a width of w and the values of the columns includes all values in the range of 1 and w, inclusive.
8. The system recited in claim 5 , wherein the parity matrix includes at least one full copy of a building block parity matrix, at least one partial copy of the building block parity matrix, and at least one copy of an identity matrix.
9. A computer program product for storing data, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
encoding a set of input data using a first error correction code to obtain a set of first codewords;
interleaving the set of first codewords;
encoding the interleaved set of first codewords using a second, systematic error correction code associated with a parity matrix having at least some columns which are linearly independent to obtain a set of second codewords, wherein the set of second codewords includes a set of second data portions and a set of second parity portions;
interleaving the set of second parity portions;
encoding the interleaved set of second parity portions using a third, systematic error correction code to obtain a set of third codewords, wherein the set of third codewords includes a set of third data portions and a set of third parity portions; and
storing, in storage, the set of first codewords and the set of third parity portions, wherein the set of second parity portions which overlaps with the set of third data portions is not stored in storage.
10. The computer program product recited in claim 9 , wherein the computer program product is configured to be utilized at least in part by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
11. The computer program product recited in claim 9 , wherein the parity matrix has a width of w and the values of the columns includes all values in the range of 1 and w, inclusive.
12. The computer program product recited in claim 9 , wherein the parity matrix includes at least one full copy of a building block parity matrix, at least one partial copy of the building block parity matrix, and at least one copy of an identity matrix.
13. A system for storing data, comprising:
means for encoding a set of input data using a first error correction code to obtain a set of first codewords;
means for interleaving the set of first codewords;
means for encoding the interleaved set of first codewords using a second, systematic error correction code associated with a parity matrix having at least some columns which are linearly independent to obtain a set of second codewords, wherein the set of second codewords includes a set of second data portions and a set of second parity portions;
means for interleaving the set of second parity portions;
means for encoding the interleaved set of second parity portions using a third, systematic error correction code to obtain a set of third codewords, wherein the set of third codewords includes a set of third data portions and a set of third parity portions; and
means for storing the set of first codewords and the set of third parity portions, wherein the set of second parity portions which overlaps with the set of third data portions is not stored in storage.
14. The system recited in claim 13 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
15. The system recited in claim 13 , wherein the parity matrix has a width of w and the values of the columns includes all values in the range of 1 and w, inclusive.
16. The system recited in claim 13 , wherein the parity matrix includes at least one full copy of a building block parity matrix, at least one partial copy of the building block parity matrix, and at least one copy of an identity matrix.