Reliability evaluation and system fail warning methods using on chip parametric monitors
A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
1. One or more computer-readable storage having instruction thereon for executing a method for monitoring a semiconductor product, comprising:
inserting at least one parametric macro onto the semiconductor product so that the parametric macro is stored within the semiconductor product, the parametric macro measuring at least a voltage level in the semiconductor product;
monitoring the at least one parametric macro to determine whether the voltage level is within a threshold amount of a level that can cause the semiconductor product to fail; and
issuing a warning that the semiconductor product is in danger of failing during use in response to the monitoring that the voltage level is within the threshold amount of the level that can cause the semiconductor product to fail.
2. The one or more computer-readable storage of claim 1 , wherein the at least one parametric macro further includes multiple parametric macros for measuring resistance, capacitance and current.
3. The one or more computer-readable storage of claim 2 , wherein the monitoring further includes monitoring the multiple parametric macros to determine whether the resistance, capacitance and current are within threshold amounts of levels that can cause the semiconductor product to fail.
4. The one or more computer-readable storage of claim 1 , further including stressing the semiconductor product.
5. The one or more computer-readable storage of claim 1 , wherein the at least one parametric macro comprises a scalable parametric macro.
6. The one or more computer-readable storage of claim 1 , wherein issuing the warning includes setting a maintenance flag in a memory location within the semiconductor product.
7. The one or more computer-readable storage of claim 1 , further including generating a parametric profile indicating how the voltage level changes over time.
8. The one or more computer-readable storage of claim 1 , further comprising creating at least one of card and system diagnostics for measurement of the at least one parametric macro.
9. The one or more computer-readable storage of claim 1 , further comprising inserting at least one of fail limits or warning levels in the at least one parametric macro.
10. The one or more computer-readable storage of claim 1 , further comprising identifying layout sensitive areas, and inserting the at least one parametric macro in the identified layout sensitive areas.
11. The one or more computer-readable storage of claim 1 , further including providing a system diagnostic mode of the semiconductor product which performs either the monitoring or stressing the semiconductor product, depending on the mode, and testing the stressed semiconductor product.
12. One or more computer-readable storage having instruction thereon for executing a method for monitoring a semiconductor product, comprising:
inserting at least one parametric macro onto the semiconductor product so that the parametric macro is stored within circuit logic in the semiconductor product, the parametric macro measuring at least one parameter on the semiconductor product that is related to failure over time of use of the semiconductor product;
monitoring the at least one parametric macro to determine whether the at least one parameter is within a threshold of a level that can cause the semiconductor product to fail; and
in response to the monitoring, issuing a warning that the semiconductor product is in danger of failing.
13. One or more computer-readable storage of claim 12 , wherein the at least one parameter includes at least one of a voltage, current, resistance or capacitance.
14. One or more computer-readable storage of claim 12 , wherein the at least one parametric macro comprises a scalable parametric macro.
15. The one or more computer-readable storage of claim 12 , further including stressing the semiconductor product.
16. The one or more computer-readable storage of claim 12 , wherein issuing the warning includes setting a maintenance flag in a memory location within the semiconductor product.
17. The one or more computer-readable storage of claim 12 , further including generating a parametric profile indicating how the at least one parameter changes over time.