IP Library Granted Patent US 8,957,434
Granted Patent B2
US 8,957,434 · App. 13/940,754 · Granted Feb 17, 2015

Light emitting device, light emitting module, and method for manufacturing light emitting device

Inventors: Yoshiaki Sugizaki (Kanagawa-ken, JP); Akihiro Kojima (Kanagawa-ken, JP); Yosuke Akimoto (Kanagawa-ken, JP); Hidefumi Yasuda (Kanagawa-ken, JP); Nozomu Takahashi (Kanagawa-ken, JP); Kazuhito Higuchi (Kanagawa-ken, JP); Susumu Obata (Kanagawa-ken, JP); Hideo Tamura (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L33/36H01L21/28H01L33/486H01L33/62H01L23/49805H01L33/50H01L33/52H01L2924/0002
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Quick Facts
Patent No.
US 8,957,434
App. No.
13/940,754
Granted
Feb 17, 2015
Kind
B2
Abstract

According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The p-side interconnect layer includes a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface. The n-side interconnect layer includes an n-side external terminal exposed from the second insulating layer at the third surface.

Claims (56)

1. A light emitting device, comprising:

a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer;

a p-side electrode provided on the second surface in a region including the light emitting layer;

an n-side electrode provided on the second surface in a region not including the light emitting layer;

a first insulating layer provided on the second surface side, the first insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode;

a p-side interconnect layer provided at least inside the first via, the p-side interconnect layer being electrically connected to the p-side electrode;

an n-side interconnect layer provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the first insulating layer, the interconnect surface being opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode; and

a second insulating layer provided at least between the p-side interconnect layer and the n-side interconnect layer,

the p-side interconnect layer including a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface,

the n-side interconnect layer including an n-side external terminal exposed from the second insulating layer at the third surface.

2. The device of claim 1 , wherein the p-side interconnect layer further includes a surface exposed from the second insulating layer other than the third surface, and the n-side interconnect layer further includes a surface exposed from the second insulating layer other than the third surface.

3. The device of claim 1 , wherein

the p-side interconnect layer includes a p-side metal plate layer and a p-side metal pillar, the p-side metal plate layer being provided at least inside the first via, the p-side metal pillar being provided on a surface of the p-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the first via and the p-side metal plate layer, and

the n-side interconnect layer includes an n-side metal plate layer and an n-side metal pillar, the n-side metal plate layer being provided inside the second via and on the interconnect surface, the n-side metal pillar being provided on a surface of the n-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the second via and the n-side metal plate layer.

4. The device of claim 1 , further comprising a transparent body provided on the first surface, the transparent body being transparent to light emitted from the light emitting layer.

5. The device of claim 1 , wherein the third surface is perpendicular to the first surface.

6. The device of claim 1 , wherein the third surface is tilted with respect to the first surface.

7. The device of claim 3 , wherein a distance between the p-side external terminal and the n-side external terminal exposed at the third surface is greater than a distance between the p-side metal plate layer and the n-side metal plate layer on the interconnect surface.

8. The device of claim 3 , wherein a planar size of the p-side metal plate layer is greater than a planar size of the p-side metal pillar.

9. The device of claim 3 , wherein the first via is provided in a plurality, and the p-side metal plate layer is connected to the p-side electrode via the plurality of the first vias.

10. The device of claim 3 , wherein the p-side metal pillar is thicker than the p-side metal plate layer.

11. The device of claim 4 , wherein the transparent body includes a transparent resin and a phosphor dispersed in the transparent resin.

12. The device of claim 4 , further comprising a reflective film provided on a side surface of the transparent body, the reflective film being reflective with respect to the light emitted from the light emitting layer.

13. The device of claim 12 , wherein the reflective film is provided also on a side surface of the first insulating layer.

14. A light emitting module, comprising:

a mounting substrate including a pad on a mounting surface; and

a light emitting device,

the light emitting device including:

a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer;

a p-side electrode provided on the second surface in a region including the light emitting layer;

an n-side electrode provided on the second surface in a region not including the light emitting layer;

a first insulating layer provided on the second surface side, the first insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode;

a p-side interconnect layer provided at least inside the first via, the p-side interconnect layer being electrically connected to the p-side electrode;

an n-side interconnect layer provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the first insulating layer, the interconnect surface being opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode; and

a second insulating layer provided at least between the p-side interconnect layer and the n-side interconnect layer,

the p-side interconnect layer including a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface,

the n-side interconnect layer including an n-side external terminal exposed from the second insulating layer at the third surface,

the light emitting device mounted on the mounting surface by bonding the p-side external terminal and the n-side external terminal to the pad,

the first surface of the light emitting device being oriented in a lateral direction with an attitude having the third surface oriented downward.

15. A method for manufacturing a light emitting device, comprising:

forming a p-side interconnect layer at least inside a first via of a stacked body including a plurality of semiconductor layers, a p-side electrode, an n-side electrode, and a first insulating layer, the plurality of semiconductor layers being divided by a dicing region, each of the plurality of semiconductor layers including a first surface, a second surface opposite to the first surface, and a light emitting layer, the p-side electrode being provided on the second surface in a region including the light emitting layer, the n-side electrode being provided on the second surface in a region not including the light emitting layer, the first insulating layer being provided on the second surface side and having the first via communicating with the p-side electrode, a second via communicating with the n-side electrode, and an interconnect surface opposite to the semiconductor layer;

forming an n-side interconnect layer apart from the p-side interconnect layer on the interconnect surface and inside the second via;

forming a second insulating layer to cover the p-side interconnect layer and the n-side interconnect layer; and

exposing one portion of the p-side interconnect layer and one portion of the n-side interconnect layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface by cutting a region including the second insulating layer, the one portion of the p-side interconnect layer, and the one portion of the n-side interconnect layer at the dicing region.

16. The method of claim 15 , wherein the one portion of the p-side interconnect layer and the one portion of the n-side interconnect layer are formed to jut onto the dicing region extending in a direction along the third surface.

17. The method of claim 15 ,

the semiconductor layer being formed on a substrate,

the method further comprising:

exposing the first surface by removing the substrate after the forming the second insulating layer; and

forming a transparent body on the exposed first surface, the transparent body being transparent to light emitted from the light emitting layer.

18. The method of claim 16 , wherein the jutting portion of the p-side interconnect layer and the n-side interconnect layer exists on both width-direction sides of the dicing region extending in the direction along the third surface.

19. The method of claim 17 , further comprising forming a reflective film on a side surface of the transparent body, the reflective film being reflective with respect to the light emitted from the light emitting layer.

20. The method of claim 19 , wherein the forming the reflective film includes:

making a trench to divide the transparent body into a plurality by cutting the transparent body at a position on the dicing region prior to the cutting the second insulating layer;

forming the reflective film on an inner wall of the trench and a top surface of the transparent body; and

removing the reflective film formed on the top surface of the transparent body.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046986/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046364/0164 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2013
From: SUGIKAZI, YOSHIAKI; KOJIMA, AKIHIRO; AKIMOTO, YOSUKE; YASUDA, HIDEFUMI; TAKAHASHI, NOZOMU; HIGUCHI, KAZUHITO; OBATA, SUSUMU; TAMURA, HIDEO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030788/0440 →
Priority Claims (1)
JP 2011-005625 · Jan 14, 2011 · national
Continuity (2)
Continuation PCTJP2011004534 · Aug 10, 2011
Related Publication 20130299864A1 · Nov 14, 2013