Semiconductor device and fabrication method
A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.
1. A method for fabricating a semiconductor device, the method comprising:
sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate;
forming a dielectric layer having an opening after the forming of the semiconductor cap layer;
forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer;
forming a gate electrode on the third semiconductor layer; and
conducting a heat treatment under a nitrogen atmosphere after the forming of the dielectric layer,
wherein the third semiconductor layer is formed after the heat treatment has been conducted under the nitrogen atmosphere.
2. The method as claimed in claim 1 , further comprising:
forming an insulating layer on the third semiconductor layer,
wherein the gate electrode is formed on the third semiconductor layer via the insulating film.
3. The method as claimed in claim 1 , wherein the p-type impurity element is magnesium (Mg).
4. The method as claimed in claim 1 , wherein the third semiconductor layer is formed by metal organic vapor phase epitaxy (MOVPE).
5. A method for fabricating a semiconductor device, the method comprising:
sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate;
forming a dielectric layer having an opening after the forming of the semiconductor cap layer;
forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer; and
forming a gate electrode on the third semiconductor layer,
wherein the forming of the third semiconductor layer includes depositing the third semiconductor layer, and conducting heat treatment under a nitrogen atmosphere after the third semiconductor layer has been deposited.
6. The method as claimed in claim 5 , further comprising:
forming an insulating layer on the third semiconductor layer,
wherein the gate electrode is formed on the third semiconductor layer via the insulating film.
7. The method as claimed in claim 5 , wherein the p-type impurity element is magnesium (Mg).
8. The method as claimed in claim 5 , wherein the third semiconductor layer is formed by metal organic vapor phase epitaxy (MOVPE).