Circuit for capacitive touch applications

1. A circuit for capacitive touch applications comprising:

a charge integrator;

a low pass-filter and a correlated double sampler sharing a common capacitor, the common capacitor acting as an input capacitor to the correlated double sampler and as a filtering capacitor to the low pass-filter;

a sampler and holder;

an analog-to-digital converter (ADC) comprising a multistage switched capacitor analog-to-digital converter having a first stage and further stages, said first stage comprising a successive approximation register and a feedback digital-to-analog converter (DAC), wherein said sampler and holder is integrated in said first stage of said analog-to-digital converter, and wherein an amplifier is shared between said sampler and holder and said first stage of said analog-to-digital converter;

said low pass-filter having a cut-off frequency lower than the Nyquist frequency of the sampler and holder; and

said low pass filter comprising said input capacitor and a serial resistor.

2. The circuit of claim 1 , wherein said low-pass filter and said correlated double sampler are integrated in a single block.

3. The circuit of claim 1 , wherein said further stages comprise a pipeline ADC or an algorithmic ADC or two or more cascaded components, each cascaded component being an algorithmic ADC.

4. The circuit of claim 1 , wherein said low pass filter, said correlated doubler sampler, said sampler and holder and said first stage of said analog to digital converter are integrated in a single block.

5. The circuit of claim 4 , wherein a capacitor is shared between said sampler and holder integrated in said first stage of said analog-to-digital converter and said single block integrating said low-pass filter and said correlated double sampler.

6. The circuit of claim 4 , wherein said single block comprises

said serial resistor connected between the output of said charge integrator and said input capacitor

said input capacitor connected between said serial resistor and an input switch

said input switch connected between said input capacitor and a virtual ground of an amplifier

said amplifier

a reset switch for said amplifier, connected between said virtual ground and the output of said amplifier

a feedback capacitor, connected between said virtual ground and a node, said node being connected to a first pre-charging switch, to a second feedback switch and a third switch, said third switch being connected to a digital to analog converter

said first pre-charging switch, said second feedback switch, said third switch and said digital to analog converter

a comparator connected to the output of said amplifier.

7. The circuit of claim 6 , wherein said amplifier integrates the functions of the amplifiers of both said correlated double sampler and said first stage of said analog to digital converter.

8. The circuit of claim 7 , further comprising

a residue capacitor connected between the virtual ground of said amplifier and a node, said node being connected to a fourth pre-charging switch and a fifth switch, said fifth switch being connected to the output of said amplifier

said fourth pre-charging switch and said fifth switch.

9. The circuit of claim 1 , wherein the circuit is part of a capacitive touch device comprising:

an array comprising a first number of rows and a second number of columns of sensing capacitors;

a generator for generating an input signal and for addressing said input signal to each of said rows at a row scan rate;

second number of the circuit.

10. The circuit of claim 9 , wherein each of the ADCs in said circuits comprises a DAC, said capacitive touch device comprising a plurality of voltage reference unit providing a plurality of reference voltages to said DACs of several ADCs of said ADCs.

11. The circuit of claim 10 , wherein said reference unit is a resistive ladder.

12. The circuit of claim 10 , wherein said reference unit includes one reference ladder that is common between said circuits and having a plurality of taps, said reference voltage being present at said taps.

13. The circuit of claim 9 , wherein said ADCs are arranged to generate a residue signal which is encoded by one or several further ADC stages.