Semiconductor devices and method of manufacturing the same

1. A semiconductor device, comprising:

active portions defined in a semiconductor substrate;

a device isolation pattern in a trench between the active portions;

a gate electrode in a gate recess region crossing the active portions and the device isolation pattern;

a gate dielectric layer between the gate electrode and an inner surface of the gate recess region; and

a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively, the first and second ohmic patterns including a metal-semiconductor compound,

wherein a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein:

the recessed top surface of the device isolation pattern at a first side of the gate recess region is between the first ohmic patterns which are on the active portions, respectively, and are adjacent to each other in a longitudinal direction of the gate electrode; and

the recessed top surface of the device isolation pattern at a second side of the gate recess region is between the second ohmic patterns which are on the active portions, respectively, and are adjacent to each other in the longitudinal direction of the gate electrode.

3. The semiconductor device of claim 1 , further comprising:

a sidewall oxide pattern on an inner sidewall and a bottom surface of the trench,

wherein the device isolation pattern is on the sidewall oxide pattern and in the trench, and

wherein a top end of the sidewall oxide pattern on the inner sidewall of the trench is higher than the recessed top surface of the device isolation pattern.

4. The semiconductor device of claim 1 , further comprising:

a capping insulating pattern on the gate electrode,

wherein a top surface of the gate electrode is at a level lower than the level of the top surface of the semiconductor substrate; and

wherein the capping insulating pattern is in the gate recess region.

5. The semiconductor device of claim 4 , wherein:

a top surface of the capping insulating pattern is at a level higher than the recessed top surface of the device isolation pattern; and

the capping insulating pattern is formed of a different insulating material from the device isolation pattern.

6. The semiconductor device of claim 4 , wherein:

a top surface of the capping insulating pattern is at substantially the same level as the recessed top surface of the device isolation pattern; and

the capping insulating pattern is formed of a same insulating material as the device isolation pattern.

7. The semiconductor device of claim 1 , wherein bottom surfaces of the first and second ohmic patterns are at a level higher than a top surface of the gate electrode.

8. The semiconductor device of claim 1 , wherein the recessed top surface of the device isolation pattern is at a level higher than a bottom end of the gate electrode.

9. The semiconductor device of claim 1 , further comprising:

isolation gates in isolation recess regions formed in the semiconductor substrate, respectively; and

an isolation gate dielectric layer between each of the isolation gates and each of the isolation recess regions,

wherein the isolation recess regions are parallel to the gate recess region, and

wherein the active portion is defined between the isolation gates adjacent to each other.

10. The semiconductor device of claim 1 , further comprising:

a source line electrically connected to the first ohmic pattern; and

a data storage part electrically connected to the second ohmic pattern.