Method for developing a custom device
A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.
1. A method for developing a custom device, the method comprising:
programming a programmable device,
wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,
wherein said interconnection layers comprise copper or aluminum,
wherein said programming comprises use of said second transistors,
wherein said programming comprises use of N type transistors and P type transistors, and
wherein said programmable device comprises at least one programmable connection; and then
a step of producing a volume device according to a specific programmed design of said programmable device,
wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, and
wherein said volume device does not have said second layer.
2. The method according to claim 1 ,
wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection.
3. The method according to claim 1 ,
wherein formation of said second transistors comprises lithography alignment to said alignment marks, and
wherein said alignment has less than 40 nm alignment error.
4. The method according to claim 1 ,
wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy.
5. The method according to claim 1 ,
wherein formation of said programmable device comprises a step of layer transfer.
6. The method according to claim 1 ,
wherein formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors.
7. The method according to claim 1 ,
wherein said second transistors are horizontally oriented.
8. A method for developing a custom device, the method comprising:
programming a programmable device,
wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,
wherein said interconnection layers comprise copper or aluminum,
wherein said programming comprises use of said second transistors,
wherein said programming comprises use of N type transistors and P type transistors,
wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy, and
wherein said programmable device comprises at least one programmable connection; and
then
a step of producing a volume device according to a specific programmed design of said programmable device,
wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, and
wherein said volume device does not have said second layer.
9. The method according to claim 8 ,
wherein said formation of said second transistors comprises lithography alignment to said alignment marks.
10. The method according to claim 8 ,
wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection.
11. The method according to claim 8 ,
wherein formation of said programmable device comprises a step of layer transfer.
12. The method according to claim 8 ,
wherein said second transistors are horizontally oriented.
13. The method according to claim 8 ,
wherein said formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors.
14. A method for developing a custom device, the method comprising:
programming a programmable device,
wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,
wherein said interconnection layers comprise copper or aluminum,
wherein said programming comprises use of said second transistors,
wherein said programming comprises use of N type transistors and P type transistors,
wherein formation of said programmable device comprises a step of layer transfer, and
wherein said programmable device comprises at least one programmable connection;
and then
a step of producing a volume device according to a specific programmed design of said programmable device,
wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, and
wherein said volume device does not have said second layer.
15. The method according to claim 14 ,
wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection.
16. The method according to claim 14 ,
wherein formation of said second transistors comprises lithography alignment to said alignment marks.
17. The method according to claim 14 ,
wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy.
18. The method according to claim 14 ,
wherein said second transistors are horizontally oriented.
19. The method according to claim 14 ,
wherein said layer transfer comprises an ion-cut.
20. The method according to claim 14 ,
wherein formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors.